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LP5569RTWR датащи(PDF) 74 Page - Texas Instruments |
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LP5569RTWR датащи(HTML) 74 Page - Texas Instruments |
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74 / 86 page ![]() 74 LP5569 SNVSAP8 – JULY 2017 www.ti.com Product Folder Links: LP5569 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Table 102. ENGINE3_MAPPING2 Register Field Descriptions (continued) Bit Field Type Reset Description 4 eng3_map_led4 R 0h 0 = LED4 is not mapped to program execution engine 3. 1 = LED4 is mapped to program execution engine 3. 3 eng3_map_led3 R 0h 0 = LED3 is not mapped to program execution engine 3. 1 = LED3 is mapped to program execution engine 3. 2 eng3_map_led2 R 0h 0 = LED2 is not mapped to program execution engine 3. 1 = LED2 is mapped to program execution engine 3. 1 eng3_map_led1 R 0h 0 = LED1 is not mapped to program execution engine 3. 1 = LED1 is mapped to program execution engine 3. 0 eng3_map_led0 R 0h 0 = LED0 is not mapped to program execution engine 3. 1 = LED0 is mapped to program execution engine 3. 8.6.1.89 PWM_CONFIG Register (Address = 80h) [reset = 4h] PWM_CONFIG is shown in Figure 108 and described in Table 103. Return to Summary Table. Figure 108. PWM_CONFIG Register 7 6 5 4 3 2 1 0 pwm_min_pulse_width RESERVED pwm_input_edg e_sel pwm_input_hysteresis R/W-0h R/W-0h R/W-0h R/W-4h Table 103. PWM_CONFIG Register Field Descriptions Bit Field Type Reset Description 7–6 pwm_min_pulse_width R/W 0h Minimum output PWM pulse width allowed. Applies to all PWM outputs. 00 = Minimum PWM pulse width = 1 clk period (100 ns, default) 01 = Minimum PWM pulse width = 2 clk periods (200 ns) 10 = Minimum PWM pulse width = 3 clk periods (300 ns) 11 = Minimum PWM pulse width = 4 clk periods (400 ns) 5–4 RESERVED R/W 0h 3 pwm_input_edge_sel R/W 0h PWM input period measurement select. 0h = PWM period is measured from rising edge to rising edge. (default) 1h = PWM period is measured from falling edge to falling edge. 2–0 pwm_input_hysteresis R/W 4h PWM input hysteresis select 0h = No hysteresis 1h = 1 LSB 2h = 2 LSBs 3h = 3 LSBs 4h = 4 LSBs (default) 5h = 5 LSBs 6h = 6 LSBs 7h = 7 LSBs 8.6.1.90 LED_FAULT1 Register (Address = 81h) [reset = 0h] LED_FAULT1 is shown in Figure 109 and described in Table 104. Return to Summary Table. Figure 109. LED_FAULT1 Register 7 6 5 4 3 2 1 0 RESERVED led_fault8 R-0h R-0h |
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