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DM505LRBABF датащи(PDF) 77 Page - Texas Instruments |
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DM505LRBABF датащи(HTML) 77 Page - Texas Instruments |
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77 / 290 page ![]() 77 DM505 www.ti.com SPRS976D – NOVEMBER 2016 – REVISED JULY 2017 Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated 5 Specifications NOTE For more information, see Power, Reset and Clock Management / PRCM Subsystem Environment / External Voltage Inputs or Initialization / Preinitialization / Power Requirements section of the Device TRM. NOTE The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in Section 4.3.8, EMIF, column "SIGNAL NAME" are not to be confused with DDR1 type of SDRAM memories. NOTE Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is still present in some clock or DPLL names. CAUTION All IO Cells are NOT Fail-safe compliant and should not be externally driven in absence of their IO supply. 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) PARAMETER(3) MIN MAX UNIT VSUPPLY (Steady-State) Supply Voltage Ranges (Steady- State) Core (vdd, vdd_dspeve) -0.3 1.5 V Analog (vdda_per, vdda_ddr_dsp, vdda_gmac_core, vdda_osc, vdda_csi, vdda_dac, vdda_adc) -0.3 2.0 V vdds_ddr1, vdds_ddr2, vdds_ddr3 (1.35V mode) -0.3 1.65 V vdds_ddr1, vdds_ddr2, vdds_ddr3 (1.5V mode) -0.3 1.8 V vdds18v, vdds18v_ddr1, vdds18v_ddr2, vdds18v_ddr3 -0.3 2.1 V vddshv1-6 (1.8V mode) -0.3 2.1 V vddshv1-6 (3.3V mode) -0.3 3.8 V VIO (Steady-State) Input and Output Voltage Ranges (Steady-State) Core I/Os -0.3 1.5 V Analog I/Os -0.3 2.0 V I/O 1.35V -0.3 1.65 V I/O 1.5V -0.3 1.8 V 1.8V I/Os -0.3 2.1 V 3.3V I/Os -0.3 3.8 V SR Maximum slew rate, all supplies 105 V/s VIO (Transient Overshoot / Undershoot) Input and Output Voltage Ranges (Transient Overshoot / Undershoot) Note: valid for up to 20% of the signal period 0.2*VDD (4) V TJ Operating junction temperature range Automotive -40 +125 °C TSTG Storage temperature range after soldered onto PC Board -55 +150 °C Latch-up I-Test I-test(5), All I/Os (if different levels then one line per level) -100 100 mA Latch-up OV-Test Over-voltage Test(6), All supplies (if different levels then one line per level) N/A 1.5*Vsup ply max V |
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