PI7C7300 datasheet(34/109 Pages) PERICOM

34 / 109 page

PI7C7300A

3-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 34 OF 109

09/25/03 Revision 1.09

The register number in address bits AD[7:2] is equal to 000000b.

The bus number is equal to the value in the secondary bus number register in

configuration space for downstream forwarding or equal to the value in the primary

bus number register in configuration space for upstream forwarding.

The bus command on CBE# is a configuration write command.

When PI7C7300A initiates the transaction on the target interface, the bus command is

changed from configuration write to special cycle. The address and data are for-warded

unchanged. Devices that use special cycles ignore the address and decode only the bus

command. The data phase contains the special cycle message. The transaction is

forwarded as a delayed transaction, but in this case the target response is not forwarded

back (because special cycles result in a master abort). Once the transaction is completed

on the target bus, through detection of the master abort condition, PI7C7300A responds

with TRDY# to the next attempt of the con-figuration transaction from the initiator. If

more than one data transfer is requested, PI7C7300A responds with a target disconnect

operation during the first data phase.

4.9

TRANSACTION TERMINATION

This section describes how PI7C7300A returns transaction termination conditions back

to the initiator. The initiator can terminate transactions with one of the following types

of termination:

Normal termination

Normal termination occurs when the initiator de-asserts FRAME# at the beginning of the

last data phase, and de-asserts IRDY# at the end of the last data phase in conjunction

with either TRDY# or STOP# assertion from the target.

Master abort

A master abort occurs when no target response is detected. When the initiator does not

detect a DEVSEL# from the target within five clock cycles after asserting FRAME#, the

initiator terminates the transaction with a master abort. If FRAME# is still asserted, the

initiator de-asserts FRAME# on the next cycle, and then de-asserts IRDY# on the

following cycle. IRDY# must be asserted in the same cycle in which FRAME# de-

asserts. If FRAME# is already de-asserted, IRDY# can be de-asserted on the next clock

cycle following detection of the master abort condition.

The target can terminate transactions with one of the following types of termination:

Normal termination

TRDY# and DEVSEL# asserted in conjunction with FRAME# de-asserted and IRDY#

asserted.

Target retry

STOP# and DEVSEL# asserted with TRDY# de-asserted during the first data phase. No

data transfers occur during the transaction. This transaction must be repeated.

Target disconnect with data transfer

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