CLC423 datasheet(5/8 Pages) NSC

5 / 8 page

http://www.national.com

Load Termination

Since the CLC423 design has been optimized for Single

Supply Operation, it is more capable of sourcing rather

than sinking current. For optimum performance, the load

should be tied to VEE. When the load is tied to VEE, the

output always sources current.

Output Overdrive Recovery

When the output range of an amplifier is exceeded, time

is required for the amplifier to recover from this over

driven condition.

Figure 5 illustrates the overload

recovery of the CLC423 when the output is overdriven.

An input was applied in an attempt to drive the output to

twice the supply rails (2 • (VCC -VEE) = 10V), but the

output limits. An inverting gain topolgy was used, see

Figure 2.

As indicated, the CLC423 recovers within

25ns on the rising edge and within 10ns on the falling

edge.

Figure 5: Overdrive Recovery

Driving Cables and Capacitive Loads

When driving cables, double termination is used to

prevent reflections. For capacitive load applications, a

small series resistor at the output of the CLC423

will improve stability and settling performance.

The

Frequency Response vs. CL plot, in the typical

performance section, gives the recommended series

resistance value for optimum flatness at various

capacitive loads.

Transmission Line Matching

One method for matching the characteristic impedance

(Zo) of a transmission line or cable is to place the

appropriate resistor at the input or output of the amplifier.

Figure 6 shows typical inverting and non-inverting circuit

configurations for matching transmission lines.

Figure 6: Transmission Line Matching

Non-inverting gain applications:

Connect Rg directly to ground.

Make R1, R2, R6, and R7 equal to Zo.

Use R3 to isolate the amplifier from reactive

loading caused by the transmission line, or

by parasitics.

Inverting gain applications:

Connect R3 directly to ground.

Make the resistors R4, R6, and R7 equal to Zo.

Make R5 II Rg = Zo.

The input and output matching resistors attenuate the

signal by a factor of 2, therefore additional gain is

needed. Use C6 to match the output transmission line

over a greater frequency range. C6 compensates for the

increase of the amplifier’s output impedance with

frequency.

Power Dissipation

Follow these steps to determine the power consumption

of the CLC423:

1. Calculate the quiescent (no-load) power:

Pamp = ICC (VCC - VEE)

2. Calculate the RMS power at the output stage:

Po = (VCC - Vload) (Iload), where Vload and

Iload are the RMS voltage and current across

the external load.

3. Calculate the total RMS power:

Pt = Pamp + Po

The maximum power that the DIP and SOIC packages

can dissipate at a given temperature is illustrated in

Figure 7. The power derating curve for any package can

be derived by utilizing the following equation:

where:

Tamb = Ambient temperature (°C)

θja = Thermal resistance, from junction to ambient, for a

given package (°C/W)

Figure 7: Power Derating Curves

Time (50ns/div)

Input

Output

CLC423

V2 +-

Ambient Temperature (

°C)

0.2

0.4

0.6

0.8

1.0

100 120 140 160 180

AJP

AJE

(175

Tamb

°−

)

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