SSC P485 PL Transceiver IC

July 1998

13

Revision 5

24000828

ADVANCE INFORMATION

Timing Diagrams

All timing values are referenced from the 50% mid-point between VDD and VSS. All output timings assume 50

pF load at the pin.

t

rst

RST_N

TS

t

dis

t

dis

t

dis

ILD

RO

Figure 10. Reset Timing

Table 1. Reset Timing Parameters

Symbol

Parameter

Min

Typ

Max

Units

Notes

Reset Pulse Width

300

-

-

ns

Output Disable Time

3

-

20

ns

1

Notes:

1.

Signals are forced asynchronously to their inactive state on reset.