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SEMICONDUCTOR TECHNICAL DATA

© Motorola, Inc. 2004

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by MPC9608

1:10 LVCMOS Zero Delay

Clock Buffer

The MPC9608 is a 3.3 V compatible, 1:10 PLL based zero-delay buffer. With a

very wide frequency range and low output skews the MPC9608 is targeted for

high performance and mid-range clock tree designs.

Features

• 1:10 outputs LVCMOS zero-delay buffer

• Single 3.3 V supply

• Supports a clock I/O frequency range of 12.5 to 200 MHz

• Selectable divide-by-two for one output bank

• Synchronous output enable control (CLK_STOP)

• Output tristate control (output high impedance)

• PLL bypass mode for low frequency system test purpose

• Supports networking, telecommunications and computer applications

• Supports a variety of microprocessors and controllers

• Compatible to PowerQuicc I and II

• Ambient Temperature Range -40

°C to +85°C

• 32-lead Pb-free package available

Functional Description

The MPC9608 uses an internal PLL and an external feedback path to lock its

low-skew clock output phase to the reference clock phase, providing virtually zero

propagation delay. This enables nested clock designs with near-zero insertion

delay. Designs using the MPC9608 as PLL fanout buffer will show significantly lower clock skew than clock distributions developed

from traditional fanout buffers. The device offers one reference clock input and two banks of 5 outputs for clock fanout. The input

frequency and phase is reproduced by the PLL and provided at the outputs. A selectable frequency divider sets the bank B outputs

to generate either an identical copy of the bank A clocks or one half of the bank A clock frequency. Both output banks remain syn-

chronized to the input reference for both bank B configurations.

Outputs are only disabled or enabled when the outputs are already in logic low state (CLK_STOP). For system test and diagnosis,

a PLL bypass mode for low frequency test purpose. In PLL bypass mode, the minimum frequency and static phase offset specification

do not apply.

losing lock.

The MPC9608 is fully 3.3 V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS sig-

nals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50

Ω transmission lines on the inci-

dent edge. For series terminated transmission lines, each of the MPC9608 outputs can drive one or two traces giving the devices an

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A

MPC9608

LOW VOLTAGE 3.3 V

LVCMOS 1:10 ZERO-DELAY

CLOCK BUFFER

AC SUFFIX

32 LEAD LQFP PACKAGE-Pb-free

CASE 873A

REV 2

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com