MPC958

ECLinPS and ECLinPS Lite

DL140 — Rev 3

3

MOTOROLA

DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

VIH

Input HIGH Voltage LVCMOS Inputs

2.0

3.6

V

VIL

Input LOW Voltage LVCMOS Inputs

0.8

V

VPP

Peak–to–Peak Input Voltage PECL_CLK

300

1000

mV

VCMR

Common Mode Range

PECL_CLK

1.0

3.0

V

Note 1.

VOH

Output HIGH Voltage

2.4

V

IOH = –20mA, Note 2.

VOL

Output LOW Voltage

0.5

V

IOL = 20mA, Note 2.

IIN

Input Current

±120

µA

CIN

Input Capacitance

4

pF

Cpd

Power Dissipation Capacitance

25

pF

Per Output

ICC

Maximum Quiescent Supply Current

75

mA

All VCC Pins

ICCPLL

Maximum PLL Supply Current

15

20

mA

VCCA Pin Only

1. VCMR is the center of the differential input signal. Normal operation is obtained when the input crosspoint is within the VCMR range and the input

swing lies within the VPP specification.

2. The MPC958 outputs can drive series or parallel terminated 50

Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications

Info section).

PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)

Symbol

Characteristic

Min

Max

Unit

Condition

fref

Reference Input Frequency

Note 3.

Note 3.

MHz

frefDC

Reference Input Duty Cycle

25

75

%

3. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

tr, tf

Output Rise/Fall Time

0.10

1.0

ns

0.8 to 2.0V

Note 4.

tpw

Output Duty Cycle

PLL Mode

tcycle/2 –

400

tcycle/2 +

400

ps

Note 4.

tsk(O)

Output–to–Output Skews (Relative to QFB)

200

ps

Note 4.

fVCO

PLL VCO Lock Range

200

400

MHz

fmax

Maximum Output Frequency

PLL Mode

(Note 4.)

PLL Mode

Bypass Mode

50

100

100

200

200

MHz

VCO_SEL = ‘1’

VCO_SEL = ‘0’

tpd(lock)

Input to Ext_FB Delay (with PLL Locked @ 100MHz)

–70

130

ps

Note 4.

tpd(bypass)

Input to Q Delay

3.0

7.0

ns

PLL Bypassed

tPLZ,HZ

Output Disable Time

7

ns

tPZL

Output Enable Time

6

ns

tjitter

Cycle–to–Cycle Jitter (Peak–to–Peak)

100

ps

Note 4.

tlock

Maximum PLL Lock Time

10

ms

4. Termination of 50

W to VCC/2.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com