LM5010 datasheet(17/19 Pages) NSC

17 / 19 page

Applications Information (Continued)

(12)

where 0.11

Ω is the minimum value of the internal resistance

from S

GND to ISEN. The next smaller standard value resistor

should be used for R

CL. With the addition of RCL it is neces-

sary to check the average and peak current values to ensure

they do not exceed the LM5010 limits. At maximum load

current the average current through the internal sense resis-

tor is:

(13)

If I

AVE is less than 2.0A no changes are necessary. If it

exceeds 2.0A, R

CL must be reduced. The upper peak of the

inductor current (I

PK+), at maximum load current, is calcu-

lated using the following:

(14)

where I

OR(max) is calculated using Equation 9. If IPK+ ex-

ceeds 3.5A , the inductor value must be increased to reduce

the ripple amplitude. This will necessitate recalculation of

OR(min),IPK-, and RCL.

When the circuit is in current limit, the upper peak current out

of the SW pin is

The inductor L1 and diode D1 must be rated for this current.

PC BOARD LAYOUT

The LM5010 regulation, over-voltage, and current limit com-

parators are very fast, and will respond to short duration

noise pulses. Layout considerations are therefore critical for

optimum performance. The layout must be as neat and

compact as possible, and all the components must be as

close as possible to their associated pins. The current loop

formed by D1, L1, C2, and the S

GND and ISEN pins should be

as small as possible. The ground connection from C2 to C1

should be as short and direct as possible. If it is expected

that the internal dissipation of the LM5010 will produce high

junction temperatures during normal operation, good use of

the PC board’s ground plane can help considerably to dissi-

pate heat. The exposed pad on the IC package bottom can

be soldered to a ground plane, and that plane should both

extend from beneath the IC, and be connected to exposed

ground plane on the board’s other side using as many vias

as possible. The exposed pad is internally connected to the

IC substrate.

The use of wide PC board traces at the pins, where possible,

can help conduct heat away from the IC. The four No Con-

nect pins on the TSSOP package are not electrically con-

nected to any part of the IC, and may be connected to

ground plane to help dissipate heat from the package. Judi-

cious positioning of the PC board within the end product,

along with the use of any available air flow (forced or natural

convection) can help reduce the junction temperature.

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