RT6158HWSC datasheet(9/12 Pages) RICHTEK

9 / 12 page

RT6158H

DS6158H-00

March 2017

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Protection

Type

Threshold Refer

to Electrical spec.

Protection Method

Shut Down Delay Time

Reset Method

OCP

IL > 6.5A

Turn on B, D MOS

CL will trigger right

away.

IL < 6.5A

UVP

VIN < 1.9V

Shutdown

100

s

VIN > 2.3V

OTP

TEMP > 160°C

Shutdown

No delay

OTP Hysteresis = 20°C

Output OVP VOUT > 5.6V

Stop switching

No delay

VOUT < 5.3V

SCP

VOUT < 1.2V

fSW become 1/4

No delay

After FAULT 40ms

Inductor Selection

The recommended power inductor is 1

μH with over 6.5A

saturation current rating. In applications, need to select

an inductor with the low DCR to provide good performance

and efficiency.

Input and Output Capacitor Selection

The input and output capacitors should be ceramic X5R

type with low ESL and ESR. The recommended input

capacitor value is 2 x 10

μF. The recommended output

capacitor value is 2 x 22

μF.

The output capacitor selection determines the output

voltage ripple and transient response. It is recommended

to use ceramic capacitors placed as close as possible to

the VOUT and GND pins of the IC. If, for any reason, the

application requires the use of large capacitors which

cannot be placed close to the IC, using a small ceramic

capacitor in parallel to the large one is recommended.

This small capacitor should be placed as close as possible

to the VOUT and GND pins of the IC. The output voltage

ripple for a given output capacitor is expressed as follows:

If the RT6158H operates in Buck mode, the worst-case

voltage ripple occurs at the highest input voltage. When

the Buck-boost operates in Boost mode, the worst-case

voltage ripple occurs at the lowest input voltage. The

maximum voltage of overshoot or undershoot, is inversely

proportional to the value of the output capacitor. For surface

mount applications, Taiyo Yuden or TDK ceramic

capacitors, X7R series Multi-layer Ceramic Capacitor is

recommended. A capacitor with a value in the range of the

calculated minimum should be used. This is required to

maintain control loop stability. There are no additional

requirements regarding minimum ESR. Low ESR

capacitors should be used to minimize output voltage

ripple. Larger capacitors will cause lower output voltage

ripple as well as lower output voltage drop during load

transients.

Thermal Considerations

The junction temperature should never exceed the

absolute maximum junction temperature TJ(MAX), listed

under Absolute Maximum Ratings, to avoid permanent

damage to the device. The maximum allowable power

dissipation depends on the thermal resistance of the IC

package, the PCB layout, the rate of surrounding airflow,

and the difference between the junction and ambient

temperatures. The maximum power dissipation can be

calculated using the following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature, TAis

the ambient temperature, and

θJA is the junction-to-ambient

thermal resistance.

For continuous operation, the maximum operating junction

temperature indicated under Recommended Operating

Conditions is 125

°C. The junction-to-ambient thermal

resistance,

θJA, is highly package dependent. For a WL-

CSP-25B 2.07x2.33 (BSC) package, the thermal

resistance,

θJA, is 35.7°C/W on a standard JEDEC 51-7

high effective-thermal-conductivity four-layer test board.

The maximum power dissipation at TA = 25

°C can be

calculated as below :

PD(MAX) = (125

°C − 25°C) / (35.7°C/W) = 2.8W for a WL-

CSP-25B 2.07x2.33 (BSC) package.

The maximum power dissipation depends on the operating

ambient temperature for the fixed TJ(MAX) and the thermal

resistance,

θJA. The derating curves in Figure 1 allows

the designer to see the effect of rising ambient temperature

on the maximum power dissipation.

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