HCPL7520 datasheet(7/15 Pages) HP

7 / 15 page

Package Characteristics

Parameter

Symbol

Min.

Typ.

Max.

Units

Test Conditions

Fig.

Note

Input-Output Momentary

VISO

3750

Vrms

TA = 25

°C, RH < 50%

Withstand Voltage

Input-Output Resistance

RI-O

>109

Ω

VI-O = 500 V

Input-Output Capacitance

CI-O

1.4

Freq = 1 MHz

Notes:

General Note: Typical values were taken from a sample of nominal units operating at nominal conditions (VDD1 = VDD2 = 5 V, VREF = 4.0 V,

Temperature = 25

°C) unless otherwise stated. Nominal plots shown from Figure 1 to 11 represented the drift of these nominal units from their

nominal operating conditions.

1. Input Offset Voltage is defined as the DC Input Voltage required to obtain an output voltage of VREF/2.

2. Gain is defined as the slope of the best-fit line of the output voltage vs. the differential input voltage (VIN+ - VIN-) over the specified input range.

Gain is derived from VREF/512 mV; e.g. VREF = 5.0, gain will be 9.77 V/V.

3. Nonlinearity is defined as half of the peak-to-peak output deviation from the best-fit gain line, expressed as a percentage of the full-scale output

voltage range.

4. NL200 is the nonlinearity specified over an input voltage range of

±200 mV.

5. NL100 is the nonlinearity specified over an input voltage range of

±100 mV.

6. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage

≥4500 Vrms for 1 second (leakage detection

current limit, II-O < 5

µA). This test is performed before the 100% production test for the partial discharge (method b) shown in

DIN EN 60747-5-2 Insulation Characteristic Table, if applicable.

7. CMRR is defined as the ratio of the differential signal gain (signal applied differentially between pins 2 and 3) to the common-mode gain (input

pins tied together and the signal applied to both inputs at the same time), expressed in dB.

Switching Specifications (AC)

Over recommended operating conditions unless otherwise specified.

Parameter

Symbol Min.

Typ.

Max.

Units

Test Conditions

Fig. Note

VIN to VOUT Signal Delay (50 – 10%) tPD10

2.2

µsVIN+ = 0 mV to 200 mV step

VIN to VOUT Signal Delay (50 – 50%) tPD50

3.4

µs

VIN to VOUT Signal Delay (50 – 90%)

tPD90

5.2

9.9

µs

VOUT Rise Time (10 – 90%)

3.0

µs

VOUT Fall Time (10 – 90%)

3.2

µs

VOUT Bandwidth (-3 dB)

100

kHz

VIN+ = 200 mVpk-pk

VOUT Noise

NOUT

31.5

mVrms VIN+ = 0 V

Common Mode Transient

CMTI

kV/

µsTA = 25°C, VCM = 1000 V

Immunity

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