CY7C66013
CY7C66113
Document #: 38-08024 Rev. *A
Page 30 of 58
During a reset, the contents the Global Interrupt Enable Register and USB End Point Interrupt Enable Register are cleared,
effectively, disabling all interrupts.
The interrupt controller contains a separate flip-flop for each interrupt. See Figure 16-3 for the logic block diagram of the interrupt
controller. When an interrupt is generated, it is first registered as a pending interrupt. It stays pending until it is serviced or a reset
occurs. A pending interrupt only generates an interrupt request if it is enabled by the corresponding bit in the interrupt enable
registers. The highest priority interrupt request is serviced following the completion of the currently executing instruction.
When servicing an interrupt, the hardware does the following:
1. Disables all interrupts by clearing the Global Interrupt Enable bit in the CPU (the state of this bit can be read at Bit 2 of the
Processor Status and Control Register, Figure 15-1).
2. Clears the flip-flop of the current interrupt.
3. Generates an automatic CALL instruction to the ROM address associated with the interrupt being serviced (i.e., the Interrupt
Vector, see Section 16.1).
The instruction in the interrupt table is typically a JMP instruction to the address of the Interrupt Service Routine (ISR). The user
can re-enable interrupts in the interrupt service routine by executing an EI instruction. Interrupts can be nested to a level limited
only by the available stack space.
The Program Counter value as well as the Carry and Zero flags (CF, ZF) are stored onto the Program Stack by the automatic
CALL instruction generated as part of the interrupt acknowledge process. The user firmware is responsible for ensuring that the
processor state is preserved and restored during an interrupt. The PUSH A instruction should typically be used as the first
command in the ISR to save the accumulator value and the POP A instruction should be used to restore the accumulator value
just before the RETI instruction. The program counter CF and ZF are restored and interrupts are enabled when the RETI
instruction is executed.
The DI and EI instructions can be used to disable and enable interrupts, respectively. These instructions affect only the Global
Interrupt Enable bit of the CPU. If desired, EI can be used to re-enable interrupts while inside an ISR, instead of waiting for the
RETI that exists the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by
examining the IRQ Sense bit (Bit 7 in the Processor Status and Control Register).
16.1
Interrupt Vectors
The Interrupt Vectors supported by the USB Controller are listed in Table 16-1. The lowest-numbered interrupt (USB Bus Reset
interrupt) has the highest priority, and the highest-numbered interrupt (I2C interrupt) has the lowest priority.
CLR
Global
Interrupt
Interrupt
Acknowledge
IRQout
USB Reset Clear Interrupt
Interrupt Priority Encoder
Enable [0]
D
Q
1
Enable
Bit
CLR
USB Reset IRQ
128-
µs CLR
128-
µs IRQ
1-ms CLR
1-ms IRQ
AddrA EP0 IRQ
AddrA EP0 CLR
I2C IRQ
Vector
Enable [6]
CLK
CLR
D
Q
CLK
1
I2C CLR
I2C Int
USB Reset Int
AddrA EP1 IRQ
AddrA EP1 CLR
IRQ Sense
IRQ
Controlled by DI, EI, and
RETI Instructions
DAC IRQ
DAC CLR
To CPU
CPU
GPIO IRQ
GPIO CLR
Hub IRQ
Hub CLR
AddrA EP2 IRQ
AddrA EP2 CLR
AddrB EP0 IRQ
AddrB EP0 CLR
AddrB EP1 IRQ
AddrB EP1 CLR
(Reg 0x20)
(Reg 0x20)
CLR
Enable [2]
D
Q
1
CLK
AddrA ENP2 Int
(Reg 0x21)
Int Enable
Sense
Figure 16-3. Interrupt Controller Function Diagram
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