CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

DS752F1

22

Figure 13. Digital Audio Port Output Timing Master Mode

Parameter

Symbol

Min

Max

Unit

DAO_MCLK period

40

—

ns

DAO_MCLK duty cycle

—

45

55

%

1. Master mode timing specifications are characterized, not production tested.

40

—

ns

—

40

60

%

2. Master mode is defined as the CS4970x4 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce

DAO_SCLK, DAO_LRCLK.

DAO_SCLK delay from DAO_MCLK rising edge,

DAO_MCLK as an input

—

19

ns

—

8ns

3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the

data is valid.

—

8ns

DAO1_DATA[3..0], DAO2_DATA[1..0]

—

10

ns

4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.

DAO_SCLK active edge to DAO_LRCLK transition

10

—

ns

DAO_LRCLK transition to DAO_SCLK active edge

10

—

ns

DAO_Dx delay from DAO_SCLK inactive edge

—

12.5

ns

DAO_MCLK

DAO_SCLK

DAO_LRCLK

DAOn_DATAn

DAO_MCLK

DAO_SCLK

DAO_LRCLK

DAOn_DATAn

Note: In these diagrams, falling edge is the inactive edge of DAO_SCLK.