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WM8521 датащи(PDF) 8 Page - Cirrus Logic

номер детали WM8521
подробное описание детали  Stereo DAC with Integrated Output Stage for 2Vrms LINE OUT
PDF  21 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8521 датащи(HTML) 8 Page - Cirrus Logic

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WM8521
Production Data
w
PD, Rev 4.2, February 2013
8
MASTER CLOCK TIMING
MCLK
t
MCLKL
t
MCLKH
t
MCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25
oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK Master clock pulse width
high
tMCLKH
11
ns
MCLK Master clock pulse width
low
tMCLKL
11
ns
MCLK Master clock cycle time
tMCLKY
28
ns
MCLK Duty cycle
40:60
60:40
Time from MCLK stopping to
digital reset
1.5
12
s
DIGITAL AUDIO INTERFACE
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25
oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
50
ns
BCLK pulse width high
tBCH
20
ns
BCLK pulse width low
tBCL
20
ns
LRCLK set-up time to BCLK
rising edge
tLRSU
10
ns
LRCLK hold time from
BCLK rising edge
tLRH
10
ns
DIN set-up time to BCLK
rising edge
tDS
10
ns
DIN hold time from BCLK
rising edge
tDH
10
ns
CLK
RCLK
CH
CL
CY
IN
RSU
S
RH
H



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