COM81C17 datasheet(11/18 Pages) SMSC

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INTERRUPT MASK REGISTER DESCRIPTION

This is an eight bit write only register which is

loaded by the processor. These bits are used to

enable interrupts from the corresponding bits in

the Status Register. This register is reset with

internal reset.

The TPUART provides unique decode capability

three

the

seven

internal

processor

accessible register.

These are the RX Buffer

only) and the Control Register (write only). The

other four registers (write only) are decoded in a

sequential manner following reset.

Refer to

table below:

Table 6 - DECODE TRUTH TABLE

nRD

nWR

nCS

READ RX BUFFER REGISTER

WRITE TO TX BUFFER

READ STATUS REGISTER

WRITE TO CONTROL

DATA BUS IN TRI STATE

The first write to address zero (RS = 0) will

access the Mode Register, the second will

access the Interrupt Mask Register, the third will

access the Baud Rate Select Register, the fourth

and all subsequent writes will access the TX

Buffer Register.

Following reset, the decode sequence of writes

to address 0 is as follows:

RS0 - Selects the Mode Control Register

RS1 - Selects the Interrupt Mask Register

RS2 - Selects the Baud Rate Select Register

RS3 - Selects the TX Buffer Register

Table 7 - INTERNAL REGISTER SELECT

RS0

RS1

RS2

RS3

AFTER RESET

AFTER FIRST WRITE

AFTER SECOND WRITE

AFTER THIRD WRITE

ALL SUBSEQUENT

WRITES

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