PLQP0048KB-B datasheet(2/177 Pages) RENESAS

2 / 177 page

R01DS0261EJ0110 Rev.1.10

Page 2 of 177

Oct 30, 2015

RX230 Group, RX231 Group

1. Overview

Overview

1.1

Outline of Specifications

Table 1.1

lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different

packages.

Table 1.1

is for products with the greatest number of functions, so the number of peripheral modules and channels will

differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different

Packages

Table 1.1

Outline of Specifications (1/4)

Classification

Module/Function

Description

CPU

 Maximum operating frequency: 54 MHz

 32-bit RX CPU (RX v2)

 Minimum instruction execution time: One instruction per clock cycle

 Address space: 4-Gbyte linear

 Register set

General purpose: Sixteen 32-bit registers

Control: Ten 32-bit registers

Accumulator: Two 72-bit registers

 Basic instructions: 75 (variable-length instruction format)

 Floating-point instructions: 11

 DSP instructions: 23

 Addressing modes: 10

 Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

 On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit

 On-chip divider: 32-bit ÷ 32-bit → 32 bits

 Barrel shifter: 32 bits

 Memory protection unit (MPU)

FPU

 Single precision (32-bit) floating point

 Data types and floating-point exceptions in conformance with the IEEE754 standard

Memory

ROM

 Capacity: 128/256/384/512 Kbytes

 Up to 32 MHz: No-wait memory access

32 to 54 MHz: Wait state required. No wait state if the instruction is served by a ROM accelerator hit.

 Programming/erasing method:

Serial programming (asynchronous serial communication/USB communication), self-programming

RAM

 Capacity: 32/64 Kbytes

 54 MHz, no-wait memory access

E2 DataFlash

 Capacity: 8 Kbytes

 Number of erase/write cycles: 1,000,000 (typ)

MCU operating mode

Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled expansion mode

(software switching)

Clock

Clock generation circuit

 Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,

PLL frequency synthesizer, USB-dedicated PLL frequency synthesizer, and IWDT-dedicated on-chip

oscillator

 Oscillation stop detection: Available

 Clock frequency accuracy measurement circuit (CAC)

 Independent settings for the system clock (ICLK), peripheral module clock (PCLK), external bus clock

(BCLK), and FlashIF clock (FCLK)

The CPU and system sections such as other bus masters run in synchronization with the system

clock (ICLK): 54 MHz (at max.)

MTU2a runs in synchronization with the PCLKA: 54 MHz (at max.)

The ADCLK for the S12AD runs in synchronization with the PCLKD: 54 MHz (at max.)

Peripheral modules other than MTU2a and S12ADE run in synchronization with the PCLKB: 32 MHz (at max.)

Devices connected to external buses run in synchronization with the BCLK: 32 MHz (at max.)

The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)

Resets

RES# pin reset, power-on reset, voltage monitoring reset, watchdog timer reset, independent watchdog

timer reset, and software reset

Voltage detection

Voltage detection circuit

(LVDAb)

 When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt

is generated.

Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels

Voltage detection circuit 1 is capable of selecting the detection voltage from 14 levels

Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels

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