S7G2 datasheet(13/116 Pages) RENESAS

13 / 116 page

R01DS0262EU0100 Rev.1.00

Page 13 of 113

Feb 23, 2016

S7G2

1. Overview

SDRAM interface

CKE

Output

SDRAM clock enable signal.

SDCS

Output

SDRAM chip select signal, active LOW.

RAS

Output

SDRAM low address strobe signal, active LOW.

CAS

Output

SDRAM column address strobe signal, active LOW.

Output

SDRAM write enable signal, active LOW.

DQM0

Output

SDRAM I/O data mask enable signal for DQ07 to DQ00.

DQM1

Output

SDRAM I/O data mask enable signal for DQ15 to DQ08.

A00 to A15

Output

Address bus.

DQ00 to DQ15

I/O

Data bus.

Interrupt

NMI

Input

Non-maskable interrupt request pin.

IRQ0 to IRQ15

Input

Maskable interrupt request pins.

GPT

GTETRGA,

GTETRGB,

GTETRGC,

GTETRGD

Input

External trigger input pins.

GTIOC0A to

GTIOC13A,

GTIOC0B to

GTIOC13B

I/O

Input capture, output compare, or PWM output pins.

GTIU

Input

Hall sensor input pin U.

GTIV

Input

Hall sensor input pin V.

GTIW

Input

Hall sensor input pin W.

GTOUUP

Output

Three-phase PWM output for BLDC motor control (positive U phase).

GTOULO

Output

Three-phase PWM output for BLDC motor control (negative U phase).

GTOVUP

Output

Three-phase PWM output for BLDC motor control (positive V phase).

GTOVLO

Output

Three-phase PWM output for BLDC motor control (negative V phase).

GTOWUP

Output

Three-phase PWM output for BLDC motor control (positive W phase).

GTOWLO

Output

Three-phase PWM output for BLDC motor control (negative W phase).

AGT

AGTEE0, AGTEE1

Input

External event input enable signals.

AGTIO0, AGTIO1

I/O

External event input and pulse output pins.

AGTO0, AGTO1

Output

Pulse output pins.

AGTOA0, AGTOA1

Output

Output compare match A output pins.

AGTOB0, AGTOB1

Output

Output compare match B output pins.

RTC

RTCOUT

Output

Output pin for 1-Hz or 64-Hz clock.

RTCIC0 to RTCIC2

Input

Time capture event input pins.

SCI

SCK0 to SCK9

I/O

Input/output pins for the clock (clock synchronous mode).

RXD0 to RXD9

Input

Input pins for received data (asynchronous mode/clock synchronous mode).

TXD0 to TXD9

Output

Output pins for transmitted data (asynchronous mode/clock synchronous

mode).

CTS0_RTS0 to

CTS9_RTS9

I/O

Input/output pins for controlling the start of transmission and reception

(asynchronous mode/clock synchronous mode), active LOW.

SCL0 to SCL9

I/O

Input/output pins for the IIC clock (simple IIC).

SDA0 to SDA9

I/O

Input/output pins for the IIC data (simple IIC).

SCK0 to SCK9

I/O

Input/output pins for the clock (simple SPI).

MISO0 to MISO9

I/O

Input/output pins for slave transmission of data (simple SPI).

MOSI0 to MOSI9

I/O

Input/output pins for master transmission of data (simple SPI).

SS0 to SS9

Input

Chip-select input pins (simple SPI), active LOW.

IIC

SCL0 to SCL2

I/O

Input/output pins for the clock.

SDA0 to SDA2

I/O

Input/output pins for data.

Table 1.16

Pin functions (2/5)

Function

Signal

I/O

Description

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