WM9710

Production Data

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PD Rev 4.0 December 2003

22

Below is a summary of each bit and its function. Only the POP, 3D, MIX, MS and LPBK bits are

supported by the WM9710. The MS bit controls the Mic selector. The LPBK bit enables loopback

of the ADC output to the DAC input without involving the AC-link, allowing for full system

performance measurements. The function default value is 0000h which is all off.

BIT

FUNCTION

POP

PCM out path and mute, 0 = pre-3D, 1 = post-3D

3D

3D stereo enhancement on/off, 1 = on

MIX

Mono output select 0 = Mix, 1 = Mic

MS

Mic select 0 = Mic1, 1 = Mic2

LPBK

ADC/DAC loopback mode

3D CONTROL REGISTER (INDEX 22H)

This register is used to control the centre and/or depth of the 3D stereo enhancement function

built into the AC’97 component. Only the depth bits DP0 to 3 have effect in the WM9710.

DP3…DP0

DEPTH

0

0%

1

-

8

Typical value

-

15

100%

Table 10 3D Control Register

POWERDOWN CONTROL/STATUS REGISTER (INDEX 26H)

This read/write register is used to program power-down states and monitor subsystem readiness.

The lower half of this register is read only status, a 1 indicating that the subsection is ready.

Ready is defined as the subsection able to perform in its nominal state. When this register is

written the bit values that come in on AC-link will have no effect on read bits 0- 7.

When the AC-link Codec Ready indicator bit (SDATAIN slot 0, bit 15) is a 1 it indicates that the

AC-link and the WM9710 control and status registers are in a fully operational state. The AC’97

controller must further probe this Powerdown Control/Status Register to determine exactly which

subsections, if any, are ready.

Note that the normal default condition of WM9710 when RESETB is applied is ‘all active’.

However, if pin 43 (PWRUP/LRC) is pulled ‘hi’ during RESETB active, all PR bits are overridden

and the device enters a low power mode. This allows a low power standby mode to be entered

without writing to the device, a condition that is desirable for example, if batteries are changed in

a PDA. The state of pin 43 is latched on the rising edge of RESETB and if the pin is ‘hi’ then the

WM9710 will remain in low power mode until register 26h is written to.

READ BIT

FUNCTION

REF

VREFs up to nominal level

ANL

Analogue mixers, etc ready

DAC

DAC section ready to accept data

ADC

ADC section ready to transmit data

Table 11 Powerdown Status Register Function

The Powerdown modes are as follows. The first three bits are to be used individually rather than

in combination with each other. The last bit PR3 can be used in combination with PR2 or by itself.

PR0 and PR1 control the PCM ADCs and DACs only. PR6 powers down just the stereo Line

Level output headphone amps on pins 39/41.

The WM9710 also includes a low power DAC to headphone mode, whereby resetting PR1and

PR6 enables the DAC and the path from the DAC to HPOUTL/R without having to power up the

main mixer (PR2). The POP bit (reg 20h) also needs to be set for this mode. The headphone

amplifier on the MONO output pin in not powered down by PR6, rather by PR2 or alternatively

may be enabled by setting MONOEN in register 74h.