ACE24AC512

Two-wire Serial EEPROM

VER 1.1

5

Figure 2: Timing diagram for output acknowledge

Device Addressing

The 2-wire serial bus protocol mandates an 8 bits device address word after a start bit condition to invoke

a valid read or write command. The first four most significant bits of the device address must be 1010,

which is common to all serial EEPROM devices. The next three bits are device address bits. These three

device address bits (5

match is made, the EEPROM device outputs an acknowledge signal after the 8

the chip will go into standby mode. However, matching may not be needed for some or all device address

bits (5

IH

then the chip goes into read mode. If a “0” is detected, the device enters programming mode.

Write Operations

(A)

Byte Write

A write operation requires two 8-bit data word address following the device address word and

acknowledge

signal. Upon receipt of this address, the EEPROM will respond with a “0” and then

clock in the first 8-bit data word.

Following receipt of the 8-bit data word, the EEPROM will again

output a “0”. The addressing device, such as a microcontroller, must terminate the write sequence

with a stop condition. At this time the EEPROM enters into an internally-timed write cycle state. All

inputs are disabled during this write cycle and the EEPROM will not respond until the writing is

completed (figure 3).

(B)

Page Write

The 512K EEPROM are capable of 128-byte page write.

A page write is initiated the same way as a byte write, but the microcontroller does not send a stop

condition after the first data word is clocked in. The microcontroller can transmit up to 127 more data