LPC2212 datasheet(21/40 Pages) PHILIPS

21 / 40 page

Philips Semiconductors

LPC2212/LPC2214

16/32-bit ARM microcontrollers with external memory interface

Product data

Rev. 02 — 23 December 2004

21 of 40

9397 750 13149

6.12 10-bit A/D converter

The LPC2212/LPC2214 each contain single 10-bit successive approximation analog

to digital converter with eight multiplexed channels.

6.12.1

Features

• Measurement range of 0 V to 3 V.

• Capable of performing more than 400,000 10-bit samples per second.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition on input pin or Timer Match signal.

6.13 UARTs

The LPC2212/LPC2214 each contain two UARTs. One UART provides a full modem

control handshake interface, the other provides only transmit and receive data lines.

6.13.1

Features

• 16 byte Receive and Transmit FIFOs.

• Register locations conform to ‘550 industry standard.

• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes

• Built-in baud rate generator.

• Standard modem interface signals included on UART1.

6.14 I2C serial I/O controller

I2C is a bi-directional bus for inter-IC control using only two wires: a serial clock line

(SCL), and a serial data line (SDA). Each device is recognized by a unique address

and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter

with the capability to both receive and send information (such as memory).

Transmitters and/or receivers can operate in either master or slave mode, depending

on whether the chip has to initiate a data transfer or is only addressed. I2C is a

multi-master bus, it can be controlled by more than one bus master connected to it.

I2C implemented in LPC2212/LPC2214 supports bit rate up to 400 kbit/s (Fast I2C).

6.14.1

Features

• Standard I2C compliant bus interface.

• Easy to conﬁgure as Master, Slave, or Master/Slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of

serial data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate

via one serial bus.

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