LM2657 datasheet(13/26 Pages) NSC

13 / 26 page

Operation Descriptions (Continued)

on both the SS pins falls below 100mV (V

SS_RESET, see

Electrical Characteristics table). Then a charging current

source I

SS_CHG of 11µA is applied at this pin to bring up the

voltage of the Soft-start capacitor gradually. This causes the

(maximum allowable) duty cycle to increase slowly, thereby

limiting the charging current into the output capacitor and

also ensuring that the inductor does not saturate. The Soft-

start capacitor will eventually charge up close to the 5V input

rail. When EN is pulled low the Soft-start capacitor is dis-

charged by the same 1.8 k

Ω internal resistor and the con-

troller is shutdown. Now the sequence is allowed to repeat

the next time EN is taken high.

One must be careful in selecting a soft start capacitor. Se-

lecting a value that is too small will cause the switcher to go

into current limit during startup. The minimum startup time

may be estimated by the capacitor charging equation:

SHUTDOWN

When the EN pin is driven low, the LM2657 initiates shut-

down by turning OFF both upper and lower FETs completely

(this occurs irrespective of FPWM or SKIP modes). See

Figure 6 for a typical shutdown plot and note that the LDRV

goes to zero (and stays there). Though not displayed, Power

Good also goes low within less than 100ns of the EN pin

going low (

∆t

SD, see Electrical Characteristics table). There-

fore in this case, the controller is NOT waiting for the output

to actually fall out of the Power Good window before it

signals Power Not Good.

When the part is shutdown with a constant current load, the

time taken for the output to decay may be calculated using

the equation

∆V/∆t = i/C. For example, there is a constant

current 2A load applied at the output and the charge stored

on the output capacitor continues to discharge into the load.

From

∆V/∆t = i/C = 2A/330µF, it can be seen that the output

voltage (say 1V) will fall to zero in about 165µs.

POWER GOOD/NOT GOOD SIGNALING

PGOOD is an open-drain output pin with an external pull-up

resistor connected to 5V. It goes high (non-conducting) when

both the outputs are within the regulation band as deter-

mined by the Power Good window detector stage on the

feedback pin (see Block Diagram). PGOOD goes low (con-

ducting) when either of the two outputs falls out of this

window. This signal is referred to as Power Not Good. A

glitch filter of 7µs filters out noise, and helps prevent spuri-

ous PGOOD responses. So Power Not Good is not asserted

until 7µs after either of the two outputs have fallen out of the

Power Good window (see

∆t

PG_NOK in Electrical Character-

istics table). During power-up/Enable/recovery from a fault,

the feedback pin voltage rises towards the regulation value.

With the feedback pin rising, there is a 20µs delay between

both the outputs being in regulation and the signaling of

Power Good (see

∆t

PG_OK

in Electrical Characteristics

table).

Power Not Good is signaled within 100ns of the Enable pin

being pulled low (see

∆t

in Electrical Characteristics

table), irrespective of the fact that the outputs could still be in

regulation. The Soft-start capacitor is also then discharged

as explained earlier.

VIN POWER-OFF (UVLO)

The LM2657 has an internal comparator that monitors Vin. If

Vin falls to approximately 4.2V, switching ceases and both

top and bottom FETs are turned OFF. ‘Power Not Good’ has

meanwhile already been signaled and a fault condition as-

serted shortly thereafter.

VDD POWER-OFF (UVLO)

If VDD falls below approximately 4V, switching ceases and

both top and bottom FETs are turned OFF. If VDD falls below

about 1.8V, the part is disabled identically to EN being pulled

low and the soft-start sequence is reset.

20134714

CH1: LDRV, CH2: Vo, CH3: SW, CH4: IL (1A/div)

Output 1V @ 2A, VIN = 10V, FPWM/SKIP, L = 10µH, f = 300kHz, COUT =

330µF

FIGURE 6. Shutdown

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