GL813 - USB2.0 CompactFlash Card Reader Controller

©2001-2002 Genesys Logic Inc.—All rights reserved.

Page 18 of 24

5.2.2 Receive Timing for Data Packet (with CRC-16)

Note that the USB 2.0 transceiver does not decode Packet ID’s (PIDs). They are passed

to the SIE for decoding.

This timing example is in HS mode. When a HS/FS UTM is in FS mode there are

approximately 40 clock cycles every byte time. The Receive State Machine assumes that

the SIE captures the data on the data bus if RXACTV and RXVLD are asserted. In FS

mode, RXVLD will only be asserted for one clock per byte time.

Note that the receive and transmit sections of the transceiver operate independently. The

receiver will receive any packets on the USB. The transceiver does not identify whether

the packet that it is receiving from the upstream or the downstream port. The SIE must

ignore receive data while it is transmitting.

Data

Data

Data

Data

CRC

CRC

PID

SYNC

PID

Data

Data

Data

Data

CRC

CRC

EOP

CLKOUT

RXACTV

Data

RXVLD

RXERR

DP/DM