MCP3221 datasheet(17/26 Pages) MICROCHIP

17 / 26 page

 2003 Microchip Technology Inc.

DS21732B-page 17

MCP3221

The input signal will initially be sampled with the first

falling edge of the clock following the transmission of a

logic-high R/W bit. Additionally, with the rising edge of

the SCL, the ADC will transmit an acknowledge bit

(ACK = 0). The master must release the data bus dur-

ing this clock pulse to allow the MCP3221 to pull the

line low (refer to Figure 5-3).

For consecutive samples, sampling begins on the fall-

ing edge of the LSB of the conversion result, which is

two bytes long. Refer to Figure 5-6 a for timing diagram.

5.3.2

READING THE CONVERSION DATA

Once the MCP3221 acknowledges the address byte,

the device will transmit four ‘0’ bits followed by the upper

four data bits of the conversion. The master device will

then acknowledge this byte with an ACK = Low. With the

following 8 clock pulses, the MCP3221 will transmit the

lower eight data bits from the conversion. The master

then sends an ACK = high, indicating to the MCP3221

that no more data is requested. The master can then

send a stop bit to end the transmission.

FIGURE 5-5:

Executing a Conversion.

5.3.3

CONSECUTIVE CONVERSIONS

For consecutive samples, sampling begins on the fall-

ing edge of the LSB of the conversion result. See

Figure 5-6 for timing.

FIGURE 5-6:

Continuous Conversion.

SDA

tACQ + tCONV is

initiated here

Address Byte

Address bits

Device bits

Upper Data Byte

0 D

Lower Data Byte

11 10

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

SCL

SDA

fSAMP = 22.3 ksps (fCLK = 400 kHz)

tACQ + tCONV is

initiated here

Address Byte

Address bits

Device bits

1 A2 A1 A0

Upper Data Byte (n)

Lower Data Byte (n)

tACQ + tCONV is

initiated here

0 D

11 10 9

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

SCL

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