AD9891 datasheet(13/58 Pages) AD

13 / 58 page

REV. A

AD9891/AD9895

–13–

the corresponding edge locations. Figure 10 shows the range

and default locations of the high speed clock signals.

H-Driver and RG Outputs

In addition to the programmable timing positions, the AD9891/

AD9895 features on-chip output drivers for the RG and H1–H4

outputs. These drivers are powerful enough to directly drive the

CCD inputs. The H-driver current can be adjusted for optimum

rise/fall time into a particular load by using the DRV Registers

(Addr x0E1 to x0E4). The RG drive current is adjustable using

the RGDRV Register (Addr x0E8). Each 3-bit DRV Register is

adjustable in 3.5 mA increments, with the minimum setting of 0

equal to OFF or three-state, and the maximum setting of 7

equal to 24.5 mA.

As shown in Figure 11, the H2 and H4 outputs are inverses of

H1 and H3, respectively. The internal propagation delay resulting

from the signal inversion is less than 1 ns, which is significantly

less than the typical rise time driving the CCD load. This results

in an H1/H2 crossover voltage at approximately 50% of the out-

put swing. The crossover voltage is not programmable.

Digital Data Outputs

The AD9891/AD9895 data output and DCLK phase are pro-

grammable using the DOUTPHASE Register (Addr x01D). Any

edge from 0 to 47 may be programmed, as shown in Figure 12.

Normally, the DOUT and DCLK signals will track in phase,

based on the DOUTPHASE Register contents. The DCLK

output phase can also be held fixed with respect to the data

outputs, by changing the DCLKMODE Register (Addr x01E)

HIGH. In this mode, the DCLK output will remain at a fixed

phase equal to CLO (the inverse of CLI) while the data output

phase is still programmable.

There is a fixed output delay from the DCLK rising edge to the

DOUT transition, called tOD. This delay can be programmed to

four values between 0 ns and 12 ns, using the DOUT_DELAY

Table I. H1–H4, RG, SHP, and SHD Timing Parameters

Length

Range

Description

POL

High/Low

Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion)

POSLOC

0–47 Edge Location

Positive Edge Location for H1, H3, and RG

Sample Location for SHP, SHD

NEGLOC

0–47 Edge Location

Negative Edge Location for H1, H3, and RG

DRV

0–7 Current Steps

Drive Current for H1–H4 and RG Outputs (3.5 mA per Step)

H1/H3

H2/H4

USING THE SAME TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING.

CCD

SIGNAL

Figure 9. 2-Phase H-Clock Operation

Table II. Precision Timing Edge Locations

Quadrant

Edge Location (Dec)

I0 to 11

0 to 11

000000 to 001011

12 to 23

16 to 27

010000 to 011011

III

24 to 35

32 to 43

100000 to 101011

36 to 47

48 to 59

110000 to 111011

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