HPC16004 datasheet(17/36 Pages) NSC

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HPC46064 Operating Modes (Continued)

TLDD11372 15

FIGURE 17 16-Bit External Memory

HPC46004 Operating Modes

EXPANDED ROMLESS MODE

Because the HPC46004 has no on-chip ROM it has only

one mode of operation the Expanded ROMless Mode The

EXM pin must be pulled high (logic ‘‘1’’) on power up the

EA bit in the PSW register should be set to a ‘‘1’’ The

HPC46004 is a ROMless device and is intended for use with

external memory The external memory may be any combi-

nation of ROM and RAM Up to 64k bytes of external mem-

ory may be accessed It is necessary to vector on reset to

an address between C000 and FFFF therefore the user

should have external memory at these addresses The EA

bit in the PSW register must immediately be set to ‘‘1’’ at the

beginning of the user’s program to disable illegal address

detection in the WATCHDOG logic

TABLE II HPC46004 Operating Modes

Operating

EXM

Memory

Mode

Bit

Configuration

Expanded ROMless

0300FFFF off-chip

Note

The on-chip RAM and Registers (000002FF) of the HPC46004 may

be accessed at all times

Wait States

The internal ROM can be accessed at the maximum operat-

ing frequency with one wait state With 0 wait states internal

ROM accesses are limited to

fC max The HPC46064

provides four software selectable Wait States that allow ac-

cess to slower memories The Wait States are selected by

the state of two bits in the PSW register Additionally the

RDY input may be used to extend the instruction cycle al-

lowing the user to interface with slow memories and periph-

erals

Power Save Modes

Two power saving modes are available on the HPC46064

HALT and IDLE In the HALT mode all processor activities

are stopped In the IDLE mode the on-board oscillator and

timer T0 are active but all other processor activities are

stopped In either mode all on-board RAM registers and

IO are unaffected

HALT MODE

The HPC46064 is placed in the HALT mode under software

control by setting bits in the PSW All processor activities

including the clock and timers are stopped In the HALT

mode power requirements for the HPC46064 are minimal

and the applied voltage (VCC) may be decreased without

altering the state of the machine There are two ways of

exiting the HALT mode via the RESET or the NMI The

RESET input reinitializes the processor Use of the NMI in-

put will generate a vectored interrupt and resume operation

from that point with no initialization The HALT mode can be

enabled or disabled by means of a control register HALT

enable To prevent accidental use of the HALT mode the

HALT enable register can be modified only once

IDLE MODE

The HPC46064 is placed in the IDLE mode through the

PSW In this mode all processor activity except the on-

board oscillator and Timer T0 is stopped As with the HALT

mode the processor is returned to full operation by the

RESET or NMI inputs but without waiting for oscillator stabi-

lization A timer T0 overflow will also cause the HPC46064

to resume normal operation

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