TLFD600

ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER

SLAS280B – MAY 2000 – REVISED NOVEMBER 2000

3

POST OFFICE BOX 655303

functional block diagram

TX DAC

FSR

FSX

SDR

SDX

SCLK

276 Ksps/

552 Ksps

Digital

HPF

Digital

LPF

25.875 kHz

138 kHz

14 Bit

4.416 Msps

TX

LPF

138 kHz

PAA

LD

RX

LPF

1104 Ksps/

2208 Ksps

ADC

PGA

LPF

Equalizer

PGA

HPF

PGA

14 Bit

4.416 Msps

0 to 9 dB

(1 dB/Step)

RX PGA3

552 kHz/

1104 kHz

180 kHz

0 to 25 dB/MHz

5 dB/MHz Step

0 to 30 dB

(3 dB/Step)

RX PGA2

–9 to +9 dB @ 6 dB/Step

+9 to 30 dB @ 3 dB/Step

RX CPGA (See Note)

AUX

Amplifiers (2)

General

Purpose I/O

Internal Reference

Clock Generator

VCXO

VCXO

DAC

0 to –24 dB

(–1 dB/Step)

TX PGA

VCXO

MCLKIN

CLK1OUT/

CLK2OUT

CLK1SEL/

CLKOUT_EN

REFM/REFP

VMID_ADC

TXBANDGAP/

RXBANDGAP

Internal Clock

GPIO0-GPIO1

GPO2-GPO5

AMPINP/

AMPINM

AMPOUTP/

AMPOUTM

RXINP/

RXINM

DRIVEROUTP/

DRIVEROUTM

DRIVERINP/

DRIVERINM

TXOUTP/

TXOUTM

552 kHz/

1104 kHz

TX Line Driver

35.328 MHz

Digital Loopback

Analog Loopback

HPF

180 kHz

DPLL

PLLSEL

NOTE: The CPGA gain range setting is related to the external components (R and C) that are connected to RXINP/M. Refer to the receiver channel

section for details.