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AM79C875KI датащи(PDF) 25 Page - Advanced Micro Devices |
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AM79C875KI датащи(HTML) 25 Page - Advanced Micro Devices |
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25 / 48 page ![]() Am79C875 25 The Physical Address of the PHY is set using the pins defined as PHYAD[4:2]. These input signals are strapped externally and sampled as reset is negated. The PHYAD[1:0] will be decoded by the NetPHY™ 4LP device to address its internal four PHY channels. All registers are available on a per port basis. Table 6. Legend for Register Tables Type Description RW Readable and writable SC Self Clearing LL Latch low until clear RO Read Only RC Cleared on the read operation LH Latch high until clear |
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