TPS2223, TPS2224, TPS2226

DUAL-SLOT CARDBUS POWER-INTERFACE SWITCHES

FOR SERIAL PCMCIA CONTROLLERS

SLVS317 – MAY 2001

21

POST OFFICE BOX 655303

APPLICATION INFORMATION

shutdown mode

In the shutdown mode, which can be controlled by SHDN or bit D8 of the input serial DATA word, each of the

xVCC and xVPP outputs is forced to a high-impedance state. In this mode, the chip quiescent current is reduced

to 1

µA or less to conserve battery power.

power-supply considerations

These switches have multiple pins for each 3.3-V and 5-V power input and for the switched xVCC outputs. Any

individual pin can conduct the rated input or output current. Unless all pins are connected in parallel, the series

resistance is higher than that specified, resulting in increased voltage drops and power loss. It is recommended

that all input and output power pins be paralleled for optimum operation.

To increase the noise immunity of the TPS2223, TPS2224 and TPS2226, the power-supply inputs should be

bypassed with at least a 4.7

µF electrolytic or tantalum capacitor paralleled by a 0.047-µF to 0.1-µF ceramic

capacitor. It is strongly recommended that the switched outputs be bypassed with a 0.1-

µF (or larger) ceramic

capacitor; doing so improves the immunity of the IC to electrostatic discharge (ESD). Care should be taken to

minimize the inductance of PCB traces between the devices and the load. High switching currents can produce

large negative voltage transients, which forward biases substrate diodes, resulting in unpredictable

performance. Similarly, no pin should be taken below –0.3 V.

RESET input

To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should

be reset at the same time as the host by applying low-impedance paths from xVCC and xVPP terminals to

ground. A low-impedance output state allows discharging of residual voltage remaining on PC Card filter

capacitance, permitting the system (host and PC Cards) to be powered up concurrently. The active low RESET

input will close internal switches S1, S4, S7, and S11 with all other switches left open. The TPS2223, TPS2224

and TPS2226 remain in the low-impedance output state until the signal is deasserted and further data is clocked

in and latched. The input serial data cannot be latched during reset mode. RESET is provided for direct

compatibility with systems that use an active-low reset voltage supervisor. The RESET pin has an internal

150-k

Ω pullup resistor.

calculating junction temperature

through 28, using an initial temperature estimate about 30

°C above ambient. Then calculate the power

dissipation for each switch, using the formula:

P

D +

r

DS(on)

I2

Next, sum the power dissipation of all switches and calculate the junction temperature:

T

J +

P

D

RqJA ) TA

Where:

Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not

within a few degrees of each other, recalculate using the calculated temperature as the initial estimate.