MP7611

Rev. 3.01

9

Figure 4. Simplified Parallel Logic Port

3-8

Decoder

3

8

8

8

To first latch bank enable

To switches across the first latch

bank for readback enable

To second latch bank enable

To reset all first latch bank

To reset all second latch bank

A0 to A2

LD1

CS

RD

LD2

R1

R2

8

Table 2. MP7611

Ideal DAC Output vs. Input Code

Hex Code

O O O O

1 F F F

) = --1.22 mV

Binary Code

16384

)

(Vr = +5 V)

00000000000000

01111111111111

16382

16384

10000000000000

16384

16384

2 O O O

) = 0

10000000000001

16386

16384

2 O O 1

) = 1.22 mV

11111111111111

32766

16384

3 F F F

) = 9.99878

Note: See Electrical Characteristics for real system accuracy