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AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial Temperature Range

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

Symbol

Pin Function

I/O

Active

Description

Address Inputs

I

N/A

Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of CLK

and

ADSC Low or ADSP Low and CE Low.

ADSC

Address Status

(Cache Controller)

I

LOW

Synchronous Addre ss Status from Cache Controller.

ADSC is an active LOW input that is used to load the

address registers with new addresses.

ADSP

Address Status

(Processor)

I

LOW

Synchronous Address Status from Processor.

ADSP is an active LOW input that is used to load the address

registers with new addresses.

ADSP is gated by CE.

ADV

Burst Address

Advance

I

LOW

Synchronous Address Advance.

ADV is an active LOW input that is used to advance the internal burst counter,

controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not

incremented; that is, there is no address advance.

BWE

Byte Write Enable

I

LOW

Synchronous byte write enable gates the byte write inputs

then

BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are

blocked and only

GW can initiate a write cycle.

Individual Byte

Write Enables

I

LOW

Synchronous byte write enables.

write causes all outputs to be disabled.

CE

Chip Enable

I

LOW

Synchronous chip enable.

AS8C403625/1825. CE also gates ADSP.

CLK

Clock

I

N/A

This is the clock input. All timing references for the device are made with respect to this input.

Chip Select 0

I

HIGH

Chip Select 1

I

LOW

Synchronous active LOW chip select.

GW

Global Write

Enable

I

LOW

Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of

CLK.

GW supersedes individual byte write enables.

Data Input/Output

I/O

N/A

Synchronous data inp ut/output (I/O) pins. The data input path is registered, triggered by the rising edge of

CLK. The data output path is flow-through (no output register).

LBO

Linear Burst Order

I

LOW

Asynchronous burst order selection input. When

LBO is HIGH, the inter-leaved burst sequence is selected.

When

LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state

while the device is operating.

OE

Output Enable

I

LOW

Asynchronous output enable. When

OE is LOW the data output drivers are enabled on the I/O pins if the chip

is also selected. When

OE is HIGH the I/O pins are in a high-impedance state.

TMS

Test ModeSelect

I

N/A

Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.

TDI

Test Data Input

I

N/A

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an

internal pullup.

TCK

Test Clock

I

N/A

Clock input of TAP co ntroller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,

while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

TDO

Test DataOutput

O

N/A

Serial output of registers placed be tween TDI and TDO. This output is active depending on the state of the

TAP controller.

TRST

JTAG Reset

(Optional)

ILOW

Optional Asynchronous JTAG rese t. Can be used to reset the TAP contro ller, but not required. JTAG reset

occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used

TRST can

be left floating. This pin has an internal pullup. Only available in BGA package.

ZZ

Sleep Mode

I

HIGH

Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the

AS8C403625/1825

to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull

down.

Power Supply

N/A

N/A

3.3V core power supply.

Power Supply

N/A

N/A

3.3V I/O Supply.

Ground

N/A

N/A

Ground.

NC

No Connect

N/A

N/A

NC pins are not electrically connected to the device.

5280 tbl 02