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ST2329B датащи(PDF) 13 Page - STMicroelectronics

номер детали ST2329B
подробное описание детали  2-bit dual supply level translator without direction control pin, open drain output
PDF  23 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST2329B датащи(HTML) 13 Page - STMicroelectronics

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DocID023359 Rev 3
13/23
ST2329B
Electrical characteristics
Table 9. AC characteristics - test conditions: VL = 2.7 - 3.6 V (device driven by open drain driver)
Table 8. AC characteristics - test conditions: VL = 2.5 - 2.7 V (device driven by open drain driver)
Symbol
Parameter
VCC = 2.7 - 3.6 V
VCC = 4.3 - 5.5 V
Unit
Min.
Max.
Min.
Max.
tRVCC
Rise time I/OVCC
70.0
50.0
ns
tFVCC
Fall time I/OVCC
14.8
19.1
ns
tRVL
Rise time I/OVL
50.0
35.0
ns
tFVL
Fall time I/OVL
9.8
10.0
ns
tI/OVL-VCC
Propagation delay time
I/OVL-LH to I/OVCC-LH
I/OVL-HL to I/OVCC-HL
tPLH
2.0
2.0
ns
tPHL
8.2
11.6
ns
tI/OVCC-VL
Propagation delay time
I/OVCC-LH to I/OVL-LH
I/OVCC-HL to I/OVL-LH
tPLH
2.0
2.0
ns
tPHL
5.3
5.9
ns
tPZL
tPLZ
Output enable and
disable time
En
6
6ns
Dis
40
40
ns
DR
Data rate(1)
2.2
3.0
MHz
1. The data rate is guaranteed based on the condition that the output I/O signal rise/fall time is less than 15% of
the input I/O signal period; the input I/O signal is at 50% duty cycle and the output I/O signal duty cycle
deviation not less than 30%.
Symbol
Parameter
VCC = 4.3-5.5V
Unit
Min.
Max.
tRVCC
Rise time I/OVCC
55.0
ns
tFVCC
Fall time I/OVCC
17.2
ns
tRVL
Rise time I/OVL
40.0
ns
tFVL
Fall time I/OVL
9.7
ns
tI/OVL-VCC
Propagation delay time
I/OVL-LH to I/OVCC-LH
I/OVL-HL to I/OVCC-HL
tPLH
2.0
ns
tPHL
10.6
ns
tI/OVCC-VL
Propagation delay time
I/OVCC-LH to I/OVL-LH
I/OVCC-HL to I/OVL-HL
tPLH
2.0
ns
tPHL
4.8
ns
tPZL
tPLZ
Output enable and disable time
En
6ns
Dis
40
ns
DR
Data rate(1)
1. The data rate is guaranteed based on the condition that the output I/O signal rise/fall time is less than 15% of
the input I/O signal period; the input I/O signal is at 50% duty cycle and the output I/O signal duty cycle
deviation not less than 30%.

3.0
MHz



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