M95040-DF datasheet(22/46 Pages) STMICROELECTRONICS

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Instructions

M950x0-W M950x0-R M950x0-DF

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DocID6512 Rev 13

6.5

Read from Memory Array (READ)

As shown in Figure 11: Read from Memory Array (READ) sequence, to send this instruction

to the device, Chip Select (S) is first driven low. The bits of the instruction byte and address

byte are then shifted in, on Serial Data Input (D). For the M95040, the most significant

address bit, A8, is incorporated as bit b3 of the instruction byte, as shown in Table 4:

Instruction set. The address is loaded into an internal address register, and the byte of data

at that address is shifted out, on Serial Data Output (Q).

If Chip Select (S) continues to be driven low, an internal bit-pointer is automatically

incremented at each clock cycle, and the corresponding data bit is shifted out.

When the highest address is reached, the address counter rolls over to zero, allowing the

Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a

single READ instruction.

The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip

Select (S) signal can occur at any time during the cycle.

The first byte addressed can be any byte within any page.

The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

Figure 11. Read from Memory Array (READ) sequence

1. Depending on the memory size, as shown in Table 7: Address range bits, the most significant address bits

are Don’t Care.

Table 7. Address range bits

Device

M95040

M95020

M95010

Address Bits

A8-A0

A7-A0

A6-A0

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