REVISION B 5/6/15

84427 DATA SHEET

9

CRYSTAL-TO-LVDS

INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER

A general LVDS interface is shown in Figure 4. In a 100

Ω dif-

ferential transmission line environment, LVDS drivers require

a matched load termination of 100

Ω across near the receiver

100 Ohm Differiential Transmission Line

R1

100

3.3V

+

-

LVDS_Driv er

3.3V

input. For a multiple LVDS outputs buffer, if only partial outputs

are used, it is recommended to terminate the un-used outputs.

Figure 5A shows a schematic example of using an 84427. In

this example, the input is a 25MHz parallel resonant crystal with

load capacitor CL=18pF. The frequency fine tuning capacitors

C1 and C2 is 22pF and 18pF respectively. This example also

shows logic control input handling. The configuration is set at

F_SEL[2:0]=101, therefore, the output frequency is 156.25MHz.

It is recommended to have one decouple capacitor per power

pin. Each decoupling capacitor should be located as close as

possible to the power pin. The low pass filter R7, C11 and C16

for clean analog supply should also be located as close to the

F_SEL0

VDD

C5

0.1u

F_SEL2

VDDA

VDD

LVDS_input

+

-

RD3

SP

VDD

VDD=3.3V

VDD

F_SEL1

C11

0.1u

C2

18p

R5

1K

(U1,16)

VDD

C3

0.1u

R1

100

VDD

RU2

SP

SP = Spare, Not Installed

(U1,24)

Zo = 50

R4

1K

F_SEL0

(U1,13)

C16

10u

RU3

1K

e.g. F_SEL[2:0]=101

Zo = 50

X1

25MHz,18pF

F_SEL2

C6

0.1u

U1

ICS84427

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Q0

nQ0

Q1

nQ1

Q2

nQ2

Q3

nQ3

Q4

nQ4

Q5

nQ5

VDD

VEE

PLL_SEL

VDD

VDDA

F_SEL2

XTAL_OUT

XTAL_IN

MR

F_SEL1

F_SEL0

VDD

RD1

SP

F_SEL1

RU1

1K

RD2

1K

C1

22p

R7

24