SLMA002 datasheet(36/55 Pages) TI1

36 / 55 page

www.ti.com

Voltage Setting

OUT1

(32)

OUT2

(33)

Compensation Capacitors

fESR(zero)

ESR

´ p ´

(34)

ZERO(desired)

ESR(zero)

(35)

(36)

ESR(zero)

´ p ´

(37)

TPS54283,, TPS54286

SLUS749C – JULY 2007 – REVISED OCTOBER 2007

The primary feedback divider resistors (R2, R9) from VOUT to FB should be between 10 k

Ω and 50 kΩ to

maintain a balance between power dissipation and noise sensitivity. For this design, 20 k

Ω is selected.

The lower resistors, R4 and R7 are found using the following equations.

• R2 = R9 = 20 kΩ

• V

FB = 0.80 V

• R4= 3.80 kΩ (3.83 kΩ standard value is used)

• R7= 6.40 kΩ (6.34 kΩ standard value is used)

Checking the ESR zero of the output capacitors:

• C = 100 µF

• ESR = 400 mΩ

• ESR

(zero) = 3980 Hz

Since the ESR zero of the main output capacitor is less than 20 kHz, an R-C filter is added in parallel with R4

and R7 to compensate for the electrolytic capacitors' ESR and add a zero about 40 kHz.

• f

ESR(zero) = 4 kHz

• f

ESR(desired)= 40 kHz

• R4 = 3.83 kΩ

• R5 = 424 Ω(422Ω selected)

• R7 = 6.34 kΩ

• R8 = 702 Ω (698Ω selected)

• R2 = R9 = 20 kΩ

• REQ1 = 3.63 kΩ

• REQ2 = 5.51 kΩ

• C8 = 10.9 nF (10 nF selected)

• C15 = 7.22 nF (6800 pF selected)

Submit Documentation Feedback

Product Folder Link(s): TPS54283 TPS54286

SLMA002 датащи(PDF) 36 Page - Texas Instruments

SLMA002 датащи(HTML) 36 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

датащи скачать

ссылки URL