STM32F779IGH7 datasheet(49/255 Pages) STMICROELECTRONICS

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DocID028294 Rev 4

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STM32F777xx STM32F778Ax STM32F779xx

Functional overview

The I/O configuration can be locked if needed by following a specific sequence in order to

avoid spurious writing to the I/Os registers.

A fast I/O handling allows a maximum I/O toggling up to 108 MHz.

2.42

Analog-to-digital converters (ADCs)

Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16

external channels, performing conversions in the single-shot or scan mode. In scan mode,

automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

•

Simultaneous sample and hold

•

Interleaved sample and hold

The ADC can be served by the DMA controller. An analog watchdog feature allows very

precise monitoring of the converted voltage of one, some or all selected channels. An

interrupt is generated when the converted voltage is outside the programmed thresholds.

To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,

TIM2, TIM3, TIM4, TIM5, or TIM8 timer.

2.43

Digital filter for Sigma-Delta Modulators (DFSDM)

The devices embed one DFSDM with 4 digital filters modules and 8 external input serial

channels (transceivers) or alternately 8 internal parallel inputs support. The DFSDM

peripheral is dedicated to interface the external Σ∆ modulators to microcontroller and then to

perform digital filtering of the received data streams (which represent analog value on Σ∆

modulators inputs). The DFSDM can also interface PDM (Pulse Density Modulation)

microphones and perform PDM to PCM conversion and filtering in hardware. The DFSDM

features optional parallel data stream inputs from microcontrollers memory (through

DMA/CPU transfers into DFSDM). The DFSDM transceivers support several serial interface

formats (to support various Σ∆ modulators). The DFSDM digital filter modules perform

digital processing according user selected filter parameters with up to 24-bit final ADC

resolution.

The DFSDM peripheral supports:

•

8 multiplexed input digital serial channels:

–

Configurable SPI interface to connect various SD modulator(s)

–

Configurable Manchester coded 1 wire interface support

–

PDM (Pulse Density Modulation) microphone input support

–

Maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)

–

Clock output for SD modulator(s): 0..20 MHz

•

Alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):

–

internal sources: device memory data streams (DMA)

•

4 digital filter modules with adjustable digital signal processing:

–

Sincxfilter: filter order/type (1..5), oversampling ratio (up to 1..1024)

–

integrator: oversampling ratio (1..256)

•

Up to 24-bit output data resolution, signed output data format

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