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STM32L471VG датащи(PDF) 173 Page - STMicroelectronics

номер детали STM32L471VG
подробное описание детали  Batch acquisition mode
PDF  218 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
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STM32L471VG датащи(HTML) 173 Page - STMicroelectronics

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STM32L471xx
Electrical characteristics
199
SPI characteristics
Unless otherwise specified, the parameters given in Table 82 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 22: General operating conditions.
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 ₓ VDD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 82. SPI characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode receiver/full duplex
2.7 < VDD < 3.6 V
Voltage Range 1
--
24
MHz
Master mode receiver/full duplex
1.71 < VDD < 3.6 V
Voltage Range 1
13
Master mode transmitter
1.71 < VDD < 3.6 V
Voltage Range 1
40
Slave mode receiver
1.71 < VDD < 3.6 V
Voltage Range 1
40
Slave mode transmitter/full duplex
2.7 < VDD < 3.6 V
Voltage Range 1
26(2)
Slave mode transmitter/full duplex
1.71 < VDD < 3.6 V
Voltage Range 1
16(2)
Voltage Range 2
13
1.08 < VDDIO2 < 1.32 V(3)
8
tsu(NSS) NSS setup time
Slave mode, SPI prescaler = 2
4ₓTPCLK
--
ns
th(NSS) NSS hold time
Slave mode, SPI prescaler = 2
2ₓTPCLK
--
ns
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
TPCLK-2
TPCLK
TPCLK+2
ns
tsu(MI)
Data input setup time
Master mode
3.5
-
-
ns
tsu(SI)
Slave mode
3
-
-
th(MI)
Data input hold time
Master mode
6.5
-
-
ns
th(SI)
Slave mode
3
-
-
ta(SO)
Data output access time Slave mode
9
-
36
ns
tdis(SO) Data output disable time Slave mode
9
-
16
ns



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