STM32L471VG datasheet(169/218 Pages) STMICROELECTRONICS

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STM32L471xx

Electrical characteristics

199

6.3.24

DFSDM characteristics

Unless otherwise specified, the parameters given in Table 77 for DFSDM are derived from

tests performed under the ambient temperature, fAPB2 frequency and VDD supply voltage

conditions summarized in Table 22: General operating conditions.

•

Output speed is set to OSPEEDRy[1:0] = 10

•

Capacitive load C = 30 pF

•

Measurement points are done at CMOS levels: 0.5 ₓ VDD

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics (DFSDM_CKINy, DFSDM_DATINy, DFSDM_CKOUT for DFSDM).

Table 77. DFSDM characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fDFSDMCLK DFSDM clock

fSYSCLK

MHz

fCKIN

(1/TCKIN)

Input clock

frequency

SPI mode (SITP[1:0] = 01)

(fDFSDMCLK/4)

fCKOUT

Output clock

frequency

MHz

DuCyCKOUT

Output clock

frequency

duty cycle

-45

twh(CKIN)

twl(CKIN)

Input clock

high and low

time

SPI mode (SITP[1:0] = 01),

External clock mode

(SPICKSEL[1:0] = 0)

TCKIN/2-0.5 TCKIN/2

tsu

Data input

setup time

SPI mode (SITP[1:0]=01),

External clock mode

(SPICKSEL[1:0] = 0)

Data input

hold time

SPI mode (SITP[1:0]=01),

External clock mode

(SPICKSEL[1:0] = 0)

TManchester

Manchester

data period

(recovered

clock period)

Manchester mode (SITP[1:0]

= 10 or 11),

Internal clock mode

(SPICKSEL[1:0] ≠ 0)

(CKOUT

DIV+1)

ₓ

TDFSDMCLK

ₓ CKOUTDIV)

ₓ TDFSDMCLK

1. Data based on characterization results, not tested in production.

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