STM32L162VC-A datasheet(29/128 Pages) STMICROELECTRONICS

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STM32L162xC/C-A

Functional overview

They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master

mode. A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SM Bus 2.0/PM Bus.

3.18.2

Universal synchronous/asynchronous receiver transmitter (USART)

The three USART interfaces are able to communicate at speeds of up to 4 Mbit/s. They

support IrDA SIR ENDEC and have LIN Master/Slave capability. The three USARTs provide

hardware management of the CTS and RTS signals and are ISO 7816 compliant.

All USART interfaces can be served by the DMA controller.

3.18.3

Serial peripheral interface (SPI)

Up to three SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in

full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode

frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC

generation/verification supports basic SD Card/MMC modes.

The SPIs can be served by the DMA controller.

3.18.4

Inter-integrated sound (I2S)

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can

operate in master or slave mode, and can be configured to operate with a 16-/32-bit

resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192

kHz are supported. When either or both of the I2S interfaces is/are configured in master

mode, the master clock can be output to the external DAC/CODEC at 256 times the

sampling frequency.

The I2Ss can be served by the DMA controller.

3.18.5

Universal serial bus (USB)

The STM32L162xC/C-A devices embed a USB device peripheral compatible with the USB

full-speed 12 Mbit/s. The USB interface implements a full-speed (12 Mbit/s) function

interface. It has software-configurable endpoint setting and supports suspend/resume. The

dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use

a HSE crystal oscillator).

3.19

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

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