STM32L151XE datasheet(20/134 Pages) STMICROELECTRONICS

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Functional overview

STM32L151xE STM32L152xE

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DocID025433 Rev 8

power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits

the POR area.

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To

reduce the power consumption in Stop mode, it is possible to automatically switch off the

internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when

VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external

reset circuit.

Note:

The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-

up time at power-on can be decreased down to 1 ms typically for devices with BOR inactive

at power-up.

The device features an embedded programmable voltage detector (PVD) that monitors the

VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different

levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An

interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when

VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate

a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.3.3

Voltage regulator

The regulator has three operation modes: main (MR), low-power (LPR) and power down.

•

MR is used in Run mode (nominal regulation)

•

LPR is used in the Low-power run, Low-power sleep and Stop modes

•

Power down is used in Standby mode. The regulator output is high impedance, the

kernel circuitry is powered down, inducing zero consumption but the contents of the

registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,

LSI, LSE crystal 32K osc, RCC_CSR).

3.3.4

Boot modes

At startup, boot pins are used to select one of three boot options:

•

Boot from Flash memory

•

Boot from System memory

•

Boot from embedded RAM

The boot from Flash usually boots at the beginning of the Flash (bank 1). An additional boot

mechanism is available through user option byte, to allow booting from bank 2 when bank 2

contains valid code. This dual boot capability can be used to easily implement a secure field

software update mechanism.

The boot loader is located in System memory. It is used to reprogram the Flash memory by

using USART1, USART2 or USB. See Application note “STM32 microcontroller system

memory boot mode” (AN2606) for details.

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