STM32L063C8 datasheet(35/121 Pages) STMICROELECTRONICS

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STM32L063x8

Functional overview

communication and modem operations (CTS/RTS). It allows multiprocessor

communication.

The LPUART has a clock domain independent from the CPU clock. It can wake up the

system from Stop mode using baudrates up to 46 Kbaud. The Wakeup events from Stop

mode are programmable and can be:



Start bit detection



Or any received data frame



Or a specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600

baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while

having an extremely low energy consumption. Higher speed clock can be used to reach

higher baudrates.

LPUART interface can be served by the DMA controller.

3.20.4

Serial peripheral interface (SPI)/Inter-integrated sound (I2S)

Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in

full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode

frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC

generation/verification supports basic SD Card/MMC modes.

The USARTs with synchronous capability can also be used as SPI master.

One standard I2S interfaces (multiplexed with SPI2) is available. It can operate in master or

slave mode, and can be configured to operate with a 16-/32-bit resolution as input or output

channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When the

I2S interfaces is configured in master mode, the master clock can be output to the external

DAC/CODEC at 256 times the sampling frequency.

The SPIs can be served by the DMA controller.

Refer to Table 13 for the differences between SPI1 and SPI2.

Table 13. SPI/I2S implementation

SPI features(1)

1. X = supported.

SPI1

SPI2

Hardware CRC calculation

I2S mode

TI mode

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