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STM32F401CD датащи(PDF) 101 Page - STMicroelectronics

номер детали STM32F401CD
подробное описание детали  Clock, reset and supply management
PDF  135 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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STM32F401CD датащи(HTML) 101 Page - STMicroelectronics

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STM32F401xD STM32F401xE
Electrical characteristics
114
Figure 34. SPI timing diagram - slave mode and CPHA = 0
Figure 35. SPI timing diagram - slave mode and CPHA = 1(1)
tv(MO)
Data output valid time
Master mode (after enable edge)
-
3
5
ns
th(MO)
Data output hold time
Master mode (after enable edge)
2
-
-
ns
1. Guaranteed by characterization, not tested in production.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%
Table 61. SPI dynamic characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ai14134c
CPHA= 0
MOSI
INPUT
MISO
OUT P UT
CPHA= 0
MS B O UT
MSB IN
BI T6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
BI T1 IN
NSS input
tSU(NSS)
tc(SCK)
th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO)
th(SO)
tr(SCK)
tf(SCK)
tdis(SO)
tsu(SI)
th(SI)
ai14135
CPHA=1
MOSI
INPUT
MISO
OUT P UT
CPHA=1
MS B O UT
MSB IN
BI T6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
BI T1 IN
tSU(NSS)
tc(SCK)
th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO)
th(SO)
tr(SCK)
tf(SCK)
tdis(SO)
tsu(SI)
th(SI)
NSS input



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