STM32F398VE datasheet(101/151 Pages) STMICROELECTRONICS

101 / 151 page

DocID027227 Rev 2

101/151

STM32F398VE

Electrical characteristics

142

PC Card/CompactFlash controller waveforms and timings

Figure 24

to Figure 29 present the PC Card/Compact Flash controller waveforms, and

Table 53

to Table 54 provide the corresponding timings. The results shown in this table are

obtained with the following FSMC configuration:



COM.FMC_SetupTime = 0x04;



COM.FMC_WaitSetupTime = 0x07;



COM.FMC_HoldSetupTime = 0x04;



COM.FMC_HiZSetupTime = 0x05;



ATT.FMC_SetupTime = 0x04;



ATT.FMC_WaitSetupTime = 0x07;



ATT.FMC_HoldSetupTime = 0x04;



ATT.FMC_HiZSetupTime = 0x05;



IO.FMC_SetupTime = 0x04;



IO.FMC_WaitSetupTime = 0x07;



IO.FMC_HoldSetupTime = 0x04;



IO.FMC_HiZSetupTime = 0x05;



TCLRSetupTime = 0;



TARSetupTime = 0.

In all timing tables, the THCLK is the HCLK clock period.

Table 52. Synchronous non-multiplexed PSRAM write timings(1)

1. Based on characterization, not tested in production

Symbol

Parameter

Min

Max

Unit

tw(CLK)

FMC_CLK period

4THCLK-1

td(CLKL-NExL)

FMC_CLK low to FMC_NEx low (x=0..2)

td(CLKH-NExH)

FMC_CLK high to FMC_NEx high



(x= 0…2)

THCLK+1.5

td(CLKL-NADVL)

FMC_CLK low to FMC_NADV low

7.5

td(CLKL-NADVH)

FMC_CLK low to FMC_NADV high

td(CLKL-AV)

FMC_CLK low to FMC_Ax valid

(x=16…25)

6.5

td(CLKH-AIV)

FMC_CLK high to FMC_Ax invalid

(x=16…25)

td(CLKL-NWEL)

FMC_CLK low to FMC_NWE low

td(CLKH-NWEH)

FMC_CLK high to FMC_NWE high

THCLK+2

td(CLKL-Data)

FMC_D[15:0] valid data after FMC_CLK

low

7.5

td(CLKL-NBLL)

FMC_CLK low to FMC_NBL low

td(CLKH-NBLH)

FMC_CLK high to FMC_NBL high

THCLK+0.5

tsu(NWAIT-CLKH)

FMC_NWAIT valid before FMC_CLK high

th(CLKH-NWAIT)

FMC_NWAIT valid after FMC_CLK high

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