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ST72361J4-Auto датащи(PDF) 67 Page - STMicroelectronics |
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ST72361J4-Auto датащи(HTML) 67 Page - STMicroelectronics |
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67 / 279 page ![]() ST72361xx-Auto Power saving modes Doc ID 12468 Rev 3 67/279 It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set and the OIE bit in the MCCSR register is cleared (see Section 10: Main clock controller with real time clock MCC/RTC for more details). Figure 29. AWUFH mode block diagram As soon as HALT mode is entered, and if the AWUEN bit has been set in the AWUCSR register, the AWU RC oscillator provides a clock signal (fAWU_RC). Its frequency is divided by a fixed divider and a programmable prescaler controlled by the AWUPR register. The output of this prescaler provides the delay time. When the delay has elapsed the AWUF flag is set by hardware and an interrupt wakes up the MCU from Halt mode. At the same time the main oscillator is immediately turned on and a 256 or 4096 cycle delay is used to stabilize it. After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU flag and its associated interrupt are cleared by software reading the AWUCSR register. To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated by measuring the clock frequency fAWU_RC and then calculating the right prescaler value. Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run mode. This connects fAWU_RC to the ICAP1 input of the 16-bit timer, allowing the fAWU_RC to be measured using the main oscillator clock as a reference time base. Similarities with halt mode The following AWUFH mode behavior is the same as normal Halt mode: ● The MCU can exit AWUFH mode by means of any interrupt with exit from Halt capability or a reset (see Section 7.4: Halt mode). ● When entering AWUFH mode, the I[1:0] bits in the CC register are forced to 10b to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. ● In AWUFH mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. None of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the AWU oscillator). ● The compatibility of Watchdog operation with AWUFH mode is configured by the WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET. AWU RC AWUFH fAWU_RC AWUFH (ei0 source) oscillator prescaler interrupt /64 divider to Timer input capture /1 .. 255 |
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