ST7262XXX datasheet(49/139 Pages) STMICROELECTRONICS

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ST7262xxx

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Doc ID 6996 Rev 5

PWM AUTO-RELOAD TIMER (Cont’d)

10.2.3 Register Description

CONTROL / STATUS REGISTER (CSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = EXCL External Clock

This bit is set and cleared by software. It selects the

input clock for the 7-bit prescaler.

0: CPU clock.

1: External clock.

Bit 6:4 = CC[2:0] Counter Clock Control

These bits are set and cleared by software. They

determine the prescaler division ratio from fINPUT.

Bit 3 = TCE Timer Counter Enable

This bit is set and cleared by software. It puts the

timer in the lowest power consumption mode.

0: Counter stopped (prescaler and counter frozen).

1: Counter running.

Bit 2 = FCRL Force Counter Re-Load

This bit is write-only and any attempt to read it will

yield a logical zero. When set, it causes the contents

of ARR register to be loaded into the counter, and

the content of the prescaler register to be cleared in

order to initialize the timer before starting to count.

Bit 1 = OIE Overflow Interrupt Enable

This bit is set and cleared by software. It allows to

enable/disable the interrupt which is generated

when the OVF bit is set.

0: Overflow Interrupt disable.

1: Overflow Interrupt enable.

Bit 0 = OVF Overflow Flag

This bit is set by hardware and cleared by software

reading the CSR register. It indicates the transition

of the counter from FFh to the ARR value.

0: New transition not yet reached

1: Transition reached

COUNTER ACCESS REGISTER (CAR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:0 = CA[7:0] Counter Access Data

These bits can be set and cleared either by hard-

ware or by software. The CAR register is used to

read or write the auto-reload counter “on the fly”

(while it is counting).

AUTO-RELOAD REGISTER (ARR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:0 = AR[7:0] Counter Auto-Reload Data

These bits are set and cleared by software. They

are used to hold the auto-reload value which is au-

tomatically loaded in the counter when an overflow

occurs. At the same time, the PWM output levels

are changed according to the corresponding OPx

bit in the PWMCR register.

This register has two PWM management func-

tions:

– Adjusting the PWM frequency

– Setting the PWM duty cycle resolution

PWM Frequency vs. Resolution:

EXCL

CC2

CC1

CC0

TCE

FCRL

OIE

OVF

fCOUNTER

With fINPUT=8 MHz CC2 CC1 CC0

fINPUT

fINPUT / 2

fINPUT / 4

fINPUT / 8

fINPUT / 16

fINPUT / 32

fINPUT / 64

fINPUT / 128

8 MHz

4 MHz

2 MHz

1 MHz

500 KHz

250 KHz

125 KHz

62.5 KHz

CA7CA6

CA5CA4

CA3CA2

CA1

CA0

AR7AR6

AR5AR4

AR3AR2

AR1

AR0

ARR value

Resolution

fPWM

Min

Max

8-bit

~0.244-KHz

31.25-KHz

[ 0..127 ]

> 7-bit

~0.244-KHz

62.5-KHz

[ 128..191 ]

> 6-bit

~0.488-KHz

125-KHz

[ 192..223 ]

> 5-bit

~0.977-KHz

250-KHz

[ 224..239 ]

> 4-bit

~1.953-KHz

500-KHz

Obsolete

Product(s)

- Obsolete

Product(s)

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