ST10F296 datasheet(230/346 Pages) STMICROELECTRONICS

230 / 346 page

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System reset

ST10F296E

230/346

20.6.1

WDTCON flags

When a bidirectional reset is enabled, a short reset may degenerate into a long reset due to

the presence of the internal filter on the RSTIN pin (see Section 20.3.1: Short and long

synchronous reset on page 221). When the RSTIN pin is released, the internal signal after

the filter (see RSTF in Figure 75 to Figure 78) is delayed, so RSTIN remains active (low) for

a while. Consequently, a short reset may be recognized as a long reset, depending on the

internal clock speed.

When either a software or watchdog bidirectional reset event occurs, the RSTIN pin is

released (at the end of the internal reset sequence), the RSTF internal signal (after the filter)

remains low for a while, and RSTIN is recognized as high or low. Eight TCL after completion

of the internal sequence, the level of the RSTF signal is sampled. If it is recognized as low, a

hardware reset sequence starts, the WDTCON register flags this event, and masks the

previous one (software or watchdog reset). Typically, a short hardware reset is recognized,

unless the RSTIN pin (and consequently the internal RSTF signal) is held sufficiently low by

the external hardware to inject a long hardware reset. The initialization routine is then

unable to recognize a software or watchdog bidirectional reset event, since a different

source is flagged inside the WDTCON register. This phenomenon does not occur when

internal Flash is selected during reset (EA = 1), since the initialization of the Flash itself

extends the internal reset duration beyond the filter delay.

Figure 85, Figure 86, and Figure 87 show the timing for software and watchdog timer

bidirectional reset events. Figure 87 shows the degeneration into a hardware reset.

Figure 85.

Software/watchdog timer bidirectional reset (EA = 1)

P0[15:13]

Not transparent

RSTF

P0[12:8]

Transparent

Not t.

P0[1:0]

Not t.

Not transparent

RST

1024 TCL

RSTOUT

(after filter)

RSTIN

≤500 ns

≥ 50 ns

≤500 ns

≥ 50 ns

IBUS-CS

7 TCL

FLARST

≤1 ms

≤2 TCL

(internal)

P0[7:2]

Not transparent

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