ST7MC1K2-Auto datasheet(222/371 Pages) STMICROELECTRONICS

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Figure 96.

Simulated demagnetization/zero-crossing event generation (SC = 0)

When using hardware commutation CH, the sequence of events needed is CH then D and finally Z events

and the value written in the registers are checked at different times.

If SDM bit is set, meaning simulated demagnetization, a value must be written in the MDREG register to

generate the simulated demagnetization. This value must be written after the C (either Cs or CH) event

preceding the simulated demagnetization.

If SZ bit is set, meaning simulated zero-crossing event, a value must be written in the MZREG register to

generate the simulated zero-crossing. This value must be written after the D event (DH or DS) preceding

the simulated zero-crossing.

When using simulated commutation (CS), the result of the 8*8 hardware multiplication of the delay

manager is not taken in account and must be overwritten if the SC bit has been set in a Z event interrupt

and the sequence of events is broken meaning that several consecutive simulated commutations can be

implemented.

As soon as the SC bit is set in the MCRC register, the system won’t necessarily expect a D event after a

C event. This can be used for an application in sensor mode with only one hall effect sensor for example.

Be careful that the D and Z events are not ignored by the peripheral, this means that for example if a Z

event occurs, the MTIM timer is reset. In simulated commutation mode, the sequence D -> Z is expected,

and this order must be respected.

As the sequence of events may not be the same when using simulated commutation, as soon as the SC

bit is set, the capture/compare feature and protection on MCOMP register is reestablished only after a

write to the MCOMP register. This means that as soon as the SC bit is set, if no write access is done to

the MCOMP register, no commutation event is generated, whatever the value of MCOMP compared to

MTIM at the time SC is set. This does not depend on the running mode: switched or autoswitched mode

(SWA bit). If software commutation event is used with a normal sequence of events C-->D-->Z, it is

After C interrupt

MDREG value checked. If

MDREG<=MTIM

immediate DS generation

After D interrupt

MZREG value checked. If

MZREG<=MTIM

immediate ZS generation

During C interrupt

simulated or hardware D/Z events

value written in MDREG/MZREG

simulated event generation

Simulated zero-crossing

Simulated demagnetization

Hardware zero-crossing

Hardware commutation

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