ST7MC1K2-Auto datasheet(221/371 Pages) STMICROELECTRONICS

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On-chip peripherals

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Note:

Commutation interrupts: It is good practice to modify the configuration for the next step as

soon as possible, that is, within the commutation interrupt routine.

All registers that need to be changed at each step have a preload register that enables the

modifications for a complete new configuration to be performed at the same time (at C event

in normal mode or when writing the MPHST register in direct access mode).

These configuration bits are:

CPB, HDM, SDM and OS2 in the MCRB register and IS[1:0], OO[5:0] in the MPHST

Note:

Initializing the MTC: As shown in Table 99 all the MTIM timer registers are in read-write

mode until the MTC clock is enabled (with the CKE bit). This allows the timer, prescaler and

compare registers to be properly initialized for start-up.

In sensorless mode, the motor has to be started in switched mode until a BEMF voltage is

present on the inputs. This means the prescaler ST[3:0] bits and MCOMP register have to

be modified by software. When running the ST[3:0] bits can only be incremented/

decremented, so the initial value is very important.

When starting directly in autoswitched mode (in sensor mode for example), write an

appropriate value in the MZREG and MZPRV register to perform a step calculation as soon

as the clock is enabled.

Built-in checks and controls for simulated events

As described in Figure 92 on page 213, MZREG, MDREG and MCOMP registers are

capture/compare registers. The compare registers are write accessible and can be used to

generate simulated events. The value of the MTIM timer is compared with the value written

in the registers and when the MTIM value reaches the corresponding register value, the

simulated event is generated. Simulated event generation is enabled when the

corresponding bits are set:

●

In the MCRB register for simulated demagnetization

–

SDM bit for simulated demagnetization.

●

In the MCRC register for simulated zero-crossing and commutation

–

SC bit for simulated commutation.

–

SZ bit for simulated zero-crossing event.

To avoid a system stop, special attention is needed when writing in the register to generate

the corresponding simulated event. The value written in the register has to be greater than

the current value of the MTIM timer when writing in the registers. If the value written in the

registers (MDREG, MZREG or MCOMP) is already less than the current value of MTIM, the

simulated event is never generated and the system is stopped.

For this reason, built-in checks and controls have been implemented in the MTIM timer.

If the value written in one of those registers in simulated event generation mode is less than

or equal to the current value of the timer when it is compared, the simulated event is

generated immediately and the value of the MTIM timer at the time the simulated event

occurs overwrites the value in the registers. Like that the value in the register really

corresponds to the simulated event generation and can be re-used to generate the next

simulated event.

So, the value written in the registers able to generate simulated events is checked by

hardware and compare to the current MTIM value to verify that it is greater.

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