ST7MC1K2-Auto datasheet(206/371 Pages) STMICROELECTRONICS

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is reset (sampling at PWM frequency) then, depending on the state of the ZSV bit in the

MSCR register, Z event sampling can run or be stopped (and D event is sampled).

When BEMF sampling is performed at the end of the PWM signal off-time, the inputs in

OFF-state are grounded or put in HiZ as selected by the DISS bit in the MSCR register.

The ZEF[3:0] event counter in the MZFR register is active in all configurations.

Figure 87.

Sampling during ON time at fSCF

Commutation noise filter

For D event detection and for Z event detection (when SPLG bit is set while DS[3:0] bits are

reset), sampling is done at fSCF during the PWM ON or OFF time (Sampling block on

page 203). To avoid any erroneous detection due to PWM commutation noise, an hardware

filter of 1µs (for fPERIPH = 4 MHz) when PWM is put ON and when PWM is put OFF has

been implemented. This means that, with sampling at 1MHz (1µs), due to this filter, 1

sample are ignored directly after the commutation.

This filter is active all the time for the D event and it is active for the Z event when the SPLG

bit is set and DS[3:0] bits are cleared (meaning that the Z event is sampled at high

frequency during the PWM ON or OFF time).

PWM OFF state

Current sample

fSCF during on time

PWM signal

DS[3:0]

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