ST7MC1K2-Auto datasheet(136/371 Pages) STMICROELECTRONICS

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10.4.7

Interrupts

Note:

The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt

mask in the CC register is reset (RIM instruction).

10.4.8

SPI registers

SPI control register (SPICR)

Table 55.

SPI interrupt control/wake-up capability

Interrupt event

Event flag

Enable control bit

Exit from WAIT

Exit from HALT

SPI end of transfer event

SPIF

SPIE

Yes

Master mode fault event

MODF

Overrun error

OVR

SPICR

Reset value: 0000 xxxx (0xh)

654

SPIE

SPE

SPR2

MSTR

CPOL

CPHA

SPR[1:0]

R/W

Table 56.

SPICR register description

Bit

Name

Function

SPIE

Serial peripheral interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SPI interrupt is generated whenever an end of transfer event, master mode

fault or overrun error occurs (SPIF = 1, MODF = 1 or OVR = 1 in the SPICSR

SPE

Serial peripheral output enable

This bit is set and cleared by software. It is also cleared by hardware when, in

master mode, SS = 0 (see Master mode fault (MODF) on page 133). The SPE bit is

cleared by reset, so the SPI peripheral is not initially connected to the external pins.

0: I/O pins free for general purpose I/O

1: SPI I/O pin alternate functions enabled

SPR2

Divider enable

This bit is set and cleared by software and is cleared by reset.

0: Divider by 2 enabled

1: Divider by 2 disabled

This bit is used with the SPR[1:0] bits to set the baud rate:

100: Serial clock = fCPU/4

000: Serial clock = fCPU/8

001: Serial clock = fCPU/16

110: Serial clock = fCPU/32

010: Serial clock = fCPU/64

011: Serial clock = fCPU/128

This bit has no effect in slave mode.

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