ST7FOXU0 datasheet(68/123 Pages) STMICROELECTRONICS

68 / 123 page

On-chip peripherals

ST7FOXU0

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Bit 7 = ICIE Interrupt Enable.

This bit is set and cleared by software.

0: Input Capture (IC) interrupt disabled

1: Input Capture (IC) interrupt enabled

Bit 6 = ICF Input Capture Flag.

This bit is set by hardware and cleared by software by reading the LTICR register. Writing to

this bit does not change the bit value.

0: No input capture

1: An input capture has occurred

Note:

After an MCU reset, software must initialize the ICF bit by reading the LTICR register

Bit 5 = TB Timebase period selection.

This bit is set and cleared by software.

0: Timebase period = tOSC * 8000 (1 ms @ 8 MHz)

1: Timebase period = tOSC * 16000 (2 ms @ 8 MHz)

Bit 4 = TBIE Timebase Interrupt enable.

This bit is set and cleared by software.

0: Timebase (TB) interrupt disabled

1: Timebase (TB) interrupt enabled

Bit 3 = TBF Timebase Interrupt Flag.

This bit is set by hardware and cleared by software reading the LTCSR register. Writing

to this bit has no effect.

0: No counter overflow

1: A counter overflow has occurred

Bit 2 = WDGRF Force Reset/ Reset Status Flag

This bit is used in two ways: it is set by software to force a watchdog reset. It is set by

hardware when a watchdog reset occurs. It can be cleared by software after a read

access to the LTCSR register.

0: No watchdog reset occurred.

1: Force a watchdog reset (write), or, a watchdog reset occurred (read).

Bit 1 = WDGE Watchdog Enable

This bit is set and cleared by software.

0: Watchdog disabled

1: Watchdog enabled

Bit 0 = WDGD Watchdog Reset Delay

This bit is set by software. It is cleared by hardware at the end of each tWDG period.

0: Watchdog reset not delayed

1: Watchdog reset delayed

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