SPC56EL54x datasheet(73/165 Pages) STMICROELECTRONICS

73 / 165 page

DocID15457 Rev 12

73/165

SPC56ELx, SPC564Lx

Package pinouts and signal descriptions

164

2.3

System pins

VSS 1V2

VSS_LV_COR



Decoupling pins for core logic. Decoupling capacitor must be

connected between these pins and the nearest VDD_LV_COR pin.

132

VSS_LV(2)

VDD 1V2

VDD_LV_COR /



Decoupling pins for core logic. Decoupling capacitor must be

connected between these pins and the nearest VDD_LV_COR pin.

—135

VDD_LV(1)

VSS 1V2

VSS_LV_COR /



Decoupling pins for core logic. Decoupling capacitor must be

connected between these pins and the nearest VDD_LV_COR pin.

—

137

VSS_LV(2)

1. VDD_LV balls are tied together on the LFBGA257 substrate.

2. VSS_LV balls are tied together on the LFBGA257 substrate.

3. VDD_HV balls are tied together on the LFBGA257 substrate.

4. VSS_HV balls are tied together on the LFBGA257 substrate.

Table 6. Supply pins (continued)

Supply

Pin #

Symbol

Description

100

pkg

144

pkg

257

pkg

Table 7. System pins

Symbol

Description

Direction

Pin #

100

pkg

144

pkg

257

pkg

Dedicated pins

MDO0(1)

Nexus Message Data Output — line

Output only

—

NMI(2)

Non Maskable Interrupt

Input only

XTAL

Input for oscillator amplifier circuit and internal clock generator

Input only

EXTAL(3)

Oscillator amplifier output

Input/Output

(4)

TMS(2)

JTAG state machine control

Input only

M16

TCK(2)

JTAG clock

Input only

L15

JCOMP(5)

JTAG compliance select

Input only

123

C10

Reset pin

RESET

Bidirectional reset with Schmitt-Trigger characteristics and

noise filter. This pin has medium drive strength. Output drive is

open drain and must be terminated by an external resistor of

value 1KOhm.(6)

Bidirectional

Test pin

VPP TEST

Pin for testing purpose only. To be tied to ground in normal

operating mode.

107

D15

1. This pad is configured for Fast (F) pad speed.

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